1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51namespace TheISA
52{
53 class ITB;
54 class DTB;
55}
56class MemObject;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63
64class RemoteGDB;
65class GDBListener;
66
67namespace TheISA
68{
69 class Predecoder;
70}
71class ThreadContext;
72class Checkpoint;
73
74namespace Trace {
75 class InstRecord;
76}
77
78
79class BaseSimpleCPU : public BaseCPU
80{
81 protected:
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::FloatReg FloatReg;
84 typedef TheISA::FloatRegBits FloatRegBits;
85
86 protected:
87 Trace::InstRecord *traceData;
88
89 public:
90 void post_interrupt(int int_num, int index);
91
92 void zero_fill_64(Addr addr) {
93 static int warned = 0;
94 if (!warned) {
95 warn ("WH64 is not implemented");
96 warned = 1;
97 }
98 };
99
100 public:
101 struct Params : public BaseCPU::Params
102 {
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51namespace TheISA
52{
53 class ITB;
54 class DTB;
55}
56class MemObject;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63
64class RemoteGDB;
65class GDBListener;
66
67namespace TheISA
68{
69 class Predecoder;
70}
71class ThreadContext;
72class Checkpoint;
73
74namespace Trace {
75 class InstRecord;
76}
77
78
79class BaseSimpleCPU : public BaseCPU
80{
81 protected:
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::FloatReg FloatReg;
84 typedef TheISA::FloatRegBits FloatRegBits;
85
86 protected:
87 Trace::InstRecord *traceData;
88
89 public:
90 void post_interrupt(int int_num, int index);
91
92 void zero_fill_64(Addr addr) {
93 static int warned = 0;
94 if (!warned) {
95 warn ("WH64 is not implemented");
96 warned = 1;
97 }
98 };
99
100 public:
101 struct Params : public BaseCPU::Params
102 {
|
107 Process *process;
108#endif
109 };
110 BaseSimpleCPU(Params *params);
111 virtual ~BaseSimpleCPU();
112
113 public:
114 /** SimpleThread object, provides all the architectural state. */
115 SimpleThread *thread;
116
117 /** ThreadContext object, provides an interface for external
118 * objects to modify this thread's state.
119 */
120 ThreadContext *tc;
121
122#if FULL_SYSTEM
123 Addr dbg_vtophys(Addr addr);
124
125 bool interval_stats;
126#endif
127
128 // current instruction
129 TheISA::MachInst inst;
130
131 // The predecoder
132 TheISA::Predecoder predecoder;
133
134 StaticInstPtr curStaticInst;
135 StaticInstPtr curMacroStaticInst;
136
137 //This is the offset from the current pc that fetch should be performed at
138 Addr fetchOffset;
139 //This flag says to stay at the current pc. This is useful for
140 //instructions which go beyond MachInst boundaries.
141 bool stayAtPC;
142
143 void checkForInterrupts();
144 Fault setupFetchRequest(Request *req);
145 void preExecute();
146 void postExecute();
147 void advancePC(Fault fault);
148
149 virtual void deallocateContext(int thread_num);
150 virtual void haltContext(int thread_num);
151
152 // statistics
153 virtual void regStats();
154 virtual void resetStats();
155
156 // number of simulated instructions
157 Counter numInst;
158 Counter startNumInst;
159 Stats::Scalar<> numInsts;
160
161 virtual Counter totalInstructions() const
162 {
163 return numInst - startNumInst;
164 }
165
166 // Mask to align PCs to MachInst sized boundaries
167 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
168
169 // number of simulated memory references
170 Stats::Scalar<> numMemRefs;
171
172 // number of simulated loads
173 Counter numLoad;
174 Counter startNumLoad;
175
176 // number of idle cycles
177 Stats::Average<> notIdleFraction;
178 Stats::Formula idleFraction;
179
180 // number of cycles stalled for I-cache responses
181 Stats::Scalar<> icacheStallCycles;
182 Counter lastIcacheStall;
183
184 // number of cycles stalled for I-cache retries
185 Stats::Scalar<> icacheRetryCycles;
186 Counter lastIcacheRetry;
187
188 // number of cycles stalled for D-cache responses
189 Stats::Scalar<> dcacheStallCycles;
190 Counter lastDcacheStall;
191
192 // number of cycles stalled for D-cache retries
193 Stats::Scalar<> dcacheRetryCycles;
194 Counter lastDcacheRetry;
195
196 virtual void serialize(std::ostream &os);
197 virtual void unserialize(Checkpoint *cp, const std::string §ion);
198
199 // These functions are only used in CPU models that split
200 // effective address computation from the actual memory access.
201 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
202 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
203 M5_DUMMY_RETURN}
204
205 void prefetch(Addr addr, unsigned flags)
206 {
207 // need to do this...
208 }
209
210 void writeHint(Addr addr, int size, unsigned flags)
211 {
212 // need to do this...
213 }
214
215
216 Fault copySrcTranslate(Addr src);
217
218 Fault copy(Addr dest);
219
220 // The register accessor methods provide the index of the
221 // instruction's operand (e.g., 0 or 1), not the architectural
222 // register index, to simplify the implementation of register
223 // renaming. We find the architectural register index by indexing
224 // into the instruction's own operand index table. Note that a
225 // raw pointer to the StaticInst is provided instead of a
226 // ref-counted StaticInstPtr to redice overhead. This is fine as
227 // long as these methods don't copy the pointer into any long-term
228 // storage (which is pretty hard to imagine they would have reason
229 // to do).
230
231 uint64_t readIntRegOperand(const StaticInst *si, int idx)
232 {
233 return thread->readIntReg(si->srcRegIdx(idx));
234 }
235
236 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
237 {
238 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
239 return thread->readFloatReg(reg_idx, width);
240 }
241
242 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
243 {
244 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
245 return thread->readFloatReg(reg_idx);
246 }
247
248 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
249 int width)
250 {
251 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
252 return thread->readFloatRegBits(reg_idx, width);
253 }
254
255 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
256 {
257 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
258 return thread->readFloatRegBits(reg_idx);
259 }
260
261 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
262 {
263 thread->setIntReg(si->destRegIdx(idx), val);
264 }
265
266 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
267 int width)
268 {
269 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
270 thread->setFloatReg(reg_idx, val, width);
271 }
272
273 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
274 {
275 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
276 thread->setFloatReg(reg_idx, val);
277 }
278
279 void setFloatRegOperandBits(const StaticInst *si, int idx,
280 FloatRegBits val, int width)
281 {
282 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
283 thread->setFloatRegBits(reg_idx, val, width);
284 }
285
286 void setFloatRegOperandBits(const StaticInst *si, int idx,
287 FloatRegBits val)
288 {
289 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
290 thread->setFloatRegBits(reg_idx, val);
291 }
292
293 uint64_t readPC() { return thread->readPC(); }
294 uint64_t readMicroPC() { return thread->readMicroPC(); }
295 uint64_t readNextPC() { return thread->readNextPC(); }
296 uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
297 uint64_t readNextNPC() { return thread->readNextNPC(); }
298
299 void setPC(uint64_t val) { thread->setPC(val); }
300 void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
301 void setNextPC(uint64_t val) { thread->setNextPC(val); }
302 void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
303 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
304
305 MiscReg readMiscRegNoEffect(int misc_reg)
306 {
307 return thread->readMiscRegNoEffect(misc_reg);
308 }
309
310 MiscReg readMiscReg(int misc_reg)
311 {
312 return thread->readMiscReg(misc_reg);
313 }
314
315 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
316 {
317 return thread->setMiscRegNoEffect(misc_reg, val);
318 }
319
320 void setMiscReg(int misc_reg, const MiscReg &val)
321 {
322 return thread->setMiscReg(misc_reg, val);
323 }
324
325 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
326 {
327 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
328 return thread->readMiscRegNoEffect(reg_idx);
329 }
330
331 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
332 {
333 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
334 return thread->readMiscReg(reg_idx);
335 }
336
337 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
338 {
339 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
340 return thread->setMiscRegNoEffect(reg_idx, val);
341 }
342
343 void setMiscRegOperand(
344 const StaticInst *si, int idx, const MiscReg &val)
345 {
346 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
347 return thread->setMiscReg(reg_idx, val);
348 }
349
350 unsigned readStCondFailures() {
351 return thread->readStCondFailures();
352 }
353
354 void setStCondFailures(unsigned sc_failures) {
355 thread->setStCondFailures(sc_failures);
356 }
357
358 MiscReg readRegOtherThread(int regIdx, int tid = -1)
359 {
360 panic("Simple CPU models do not support multithreaded "
361 "register access.\n");
362 }
363
364 void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
365 {
366 panic("Simple CPU models do not support multithreaded "
367 "register access.\n");
368 }
369
370#if FULL_SYSTEM
371 Fault hwrei() { return thread->hwrei(); }
372 void ev5_trap(Fault fault) { fault->invoke(tc); }
373 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
374#else
375 void syscall(int64_t callnum) { thread->syscall(callnum); }
376#endif
377
378 bool misspeculating() { return thread->misspeculating(); }
379 ThreadContext *tcBase() { return tc; }
380};
381
382#endif // __CPU_SIMPLE_BASE_HH__
| 106 Process *process;
107#endif
108 };
109 BaseSimpleCPU(Params *params);
110 virtual ~BaseSimpleCPU();
111
112 public:
113 /** SimpleThread object, provides all the architectural state. */
114 SimpleThread *thread;
115
116 /** ThreadContext object, provides an interface for external
117 * objects to modify this thread's state.
118 */
119 ThreadContext *tc;
120
121#if FULL_SYSTEM
122 Addr dbg_vtophys(Addr addr);
123
124 bool interval_stats;
125#endif
126
127 // current instruction
128 TheISA::MachInst inst;
129
130 // The predecoder
131 TheISA::Predecoder predecoder;
132
133 StaticInstPtr curStaticInst;
134 StaticInstPtr curMacroStaticInst;
135
136 //This is the offset from the current pc that fetch should be performed at
137 Addr fetchOffset;
138 //This flag says to stay at the current pc. This is useful for
139 //instructions which go beyond MachInst boundaries.
140 bool stayAtPC;
141
142 void checkForInterrupts();
143 Fault setupFetchRequest(Request *req);
144 void preExecute();
145 void postExecute();
146 void advancePC(Fault fault);
147
148 virtual void deallocateContext(int thread_num);
149 virtual void haltContext(int thread_num);
150
151 // statistics
152 virtual void regStats();
153 virtual void resetStats();
154
155 // number of simulated instructions
156 Counter numInst;
157 Counter startNumInst;
158 Stats::Scalar<> numInsts;
159
160 virtual Counter totalInstructions() const
161 {
162 return numInst - startNumInst;
163 }
164
165 // Mask to align PCs to MachInst sized boundaries
166 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
167
168 // number of simulated memory references
169 Stats::Scalar<> numMemRefs;
170
171 // number of simulated loads
172 Counter numLoad;
173 Counter startNumLoad;
174
175 // number of idle cycles
176 Stats::Average<> notIdleFraction;
177 Stats::Formula idleFraction;
178
179 // number of cycles stalled for I-cache responses
180 Stats::Scalar<> icacheStallCycles;
181 Counter lastIcacheStall;
182
183 // number of cycles stalled for I-cache retries
184 Stats::Scalar<> icacheRetryCycles;
185 Counter lastIcacheRetry;
186
187 // number of cycles stalled for D-cache responses
188 Stats::Scalar<> dcacheStallCycles;
189 Counter lastDcacheStall;
190
191 // number of cycles stalled for D-cache retries
192 Stats::Scalar<> dcacheRetryCycles;
193 Counter lastDcacheRetry;
194
195 virtual void serialize(std::ostream &os);
196 virtual void unserialize(Checkpoint *cp, const std::string §ion);
197
198 // These functions are only used in CPU models that split
199 // effective address computation from the actual memory access.
200 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
201 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
202 M5_DUMMY_RETURN}
203
204 void prefetch(Addr addr, unsigned flags)
205 {
206 // need to do this...
207 }
208
209 void writeHint(Addr addr, int size, unsigned flags)
210 {
211 // need to do this...
212 }
213
214
215 Fault copySrcTranslate(Addr src);
216
217 Fault copy(Addr dest);
218
219 // The register accessor methods provide the index of the
220 // instruction's operand (e.g., 0 or 1), not the architectural
221 // register index, to simplify the implementation of register
222 // renaming. We find the architectural register index by indexing
223 // into the instruction's own operand index table. Note that a
224 // raw pointer to the StaticInst is provided instead of a
225 // ref-counted StaticInstPtr to redice overhead. This is fine as
226 // long as these methods don't copy the pointer into any long-term
227 // storage (which is pretty hard to imagine they would have reason
228 // to do).
229
230 uint64_t readIntRegOperand(const StaticInst *si, int idx)
231 {
232 return thread->readIntReg(si->srcRegIdx(idx));
233 }
234
235 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
236 {
237 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
238 return thread->readFloatReg(reg_idx, width);
239 }
240
241 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
242 {
243 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
244 return thread->readFloatReg(reg_idx);
245 }
246
247 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
248 int width)
249 {
250 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
251 return thread->readFloatRegBits(reg_idx, width);
252 }
253
254 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
255 {
256 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
257 return thread->readFloatRegBits(reg_idx);
258 }
259
260 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
261 {
262 thread->setIntReg(si->destRegIdx(idx), val);
263 }
264
265 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
266 int width)
267 {
268 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
269 thread->setFloatReg(reg_idx, val, width);
270 }
271
272 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
273 {
274 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
275 thread->setFloatReg(reg_idx, val);
276 }
277
278 void setFloatRegOperandBits(const StaticInst *si, int idx,
279 FloatRegBits val, int width)
280 {
281 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
282 thread->setFloatRegBits(reg_idx, val, width);
283 }
284
285 void setFloatRegOperandBits(const StaticInst *si, int idx,
286 FloatRegBits val)
287 {
288 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
289 thread->setFloatRegBits(reg_idx, val);
290 }
291
292 uint64_t readPC() { return thread->readPC(); }
293 uint64_t readMicroPC() { return thread->readMicroPC(); }
294 uint64_t readNextPC() { return thread->readNextPC(); }
295 uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
296 uint64_t readNextNPC() { return thread->readNextNPC(); }
297
298 void setPC(uint64_t val) { thread->setPC(val); }
299 void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
300 void setNextPC(uint64_t val) { thread->setNextPC(val); }
301 void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
302 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
303
304 MiscReg readMiscRegNoEffect(int misc_reg)
305 {
306 return thread->readMiscRegNoEffect(misc_reg);
307 }
308
309 MiscReg readMiscReg(int misc_reg)
310 {
311 return thread->readMiscReg(misc_reg);
312 }
313
314 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
315 {
316 return thread->setMiscRegNoEffect(misc_reg, val);
317 }
318
319 void setMiscReg(int misc_reg, const MiscReg &val)
320 {
321 return thread->setMiscReg(misc_reg, val);
322 }
323
324 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
325 {
326 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
327 return thread->readMiscRegNoEffect(reg_idx);
328 }
329
330 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
331 {
332 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
333 return thread->readMiscReg(reg_idx);
334 }
335
336 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
337 {
338 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
339 return thread->setMiscRegNoEffect(reg_idx, val);
340 }
341
342 void setMiscRegOperand(
343 const StaticInst *si, int idx, const MiscReg &val)
344 {
345 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
346 return thread->setMiscReg(reg_idx, val);
347 }
348
349 unsigned readStCondFailures() {
350 return thread->readStCondFailures();
351 }
352
353 void setStCondFailures(unsigned sc_failures) {
354 thread->setStCondFailures(sc_failures);
355 }
356
357 MiscReg readRegOtherThread(int regIdx, int tid = -1)
358 {
359 panic("Simple CPU models do not support multithreaded "
360 "register access.\n");
361 }
362
363 void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
364 {
365 panic("Simple CPU models do not support multithreaded "
366 "register access.\n");
367 }
368
369#if FULL_SYSTEM
370 Fault hwrei() { return thread->hwrei(); }
371 void ev5_trap(Fault fault) { fault->invoke(tc); }
372 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
373#else
374 void syscall(int64_t callnum) { thread->syscall(callnum); }
375#endif
376
377 bool misspeculating() { return thread->misspeculating(); }
378 ThreadContext *tcBase() { return tc; }
379};
380
381#endif // __CPU_SIMPLE_BASE_HH__
|