1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51namespace TheISA
52{
53 class ITB;
54 class DTB;
55}
56class MemObject;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63
64class RemoteGDB;
65class GDBListener;
66
67namespace TheISA
68{
69 class Predecoder;
70}
71class ThreadContext;
72class Checkpoint;
73
74namespace Trace {
75 class InstRecord;
76}
77
78
79class BaseSimpleCPU : public BaseCPU
80{
81 protected:
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::FloatReg FloatReg;
84 typedef TheISA::FloatRegBits FloatRegBits;
85
86 protected:
87 Trace::InstRecord *traceData;
88
89 public:
90 void post_interrupt(int int_num, int index);
91
92 void zero_fill_64(Addr addr) {
93 static int warned = 0;
94 if (!warned) {
95 warn ("WH64 is not implemented");
96 warned = 1;
97 }
98 };
99
100 public:
101 struct Params : public BaseCPU::Params
102 {
103#if FULL_SYSTEM
104 TheISA::ITB *itb;
105 TheISA::DTB *dtb;
106#else
107 Process *process;
108#endif
109 };
110 BaseSimpleCPU(Params *params);
111 virtual ~BaseSimpleCPU();
112
113 public:
114 /** SimpleThread object, provides all the architectural state. */
115 SimpleThread *thread;
116
117 /** ThreadContext object, provides an interface for external
118 * objects to modify this thread's state.
119 */
120 ThreadContext *tc;
121
122#if FULL_SYSTEM
123 Addr dbg_vtophys(Addr addr);
124
125 bool interval_stats;
126#endif
127
128 // current instruction
129 TheISA::MachInst inst;
130
131 // The predecoder
132 TheISA::Predecoder predecoder;
133
134 // Static data storage
135 TheISA::LargestRead dataReg;
136
137 StaticInstPtr curStaticInst;
138 StaticInstPtr curMacroStaticInst;
139
140 //This is the offset from the current pc that fetch should be performed at
141 Addr fetchOffset;
142 //This flag says to stay at the current pc. This is useful for
143 //instructions which go beyond MachInst boundaries.
144 bool stayAtPC;
145
146 void checkForInterrupts();
147 Fault setupFetchRequest(Request *req);
148 void preExecute();
149 void postExecute();
150 void advancePC(Fault fault);
151
152 virtual void deallocateContext(int thread_num);
153 virtual void haltContext(int thread_num);
154
155 // statistics
156 virtual void regStats();
157 virtual void resetStats();
158
159 // number of simulated instructions
160 Counter numInst;
161 Counter startNumInst;
162 Stats::Scalar<> numInsts;
163
164 virtual Counter totalInstructions() const
165 {
166 return numInst - startNumInst;
167 }
168
169 // Mask to align PCs to MachInst sized boundaries
170 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
171
172 // number of simulated memory references
173 Stats::Scalar<> numMemRefs;
174
175 // number of simulated loads
176 Counter numLoad;
177 Counter startNumLoad;
178
179 // number of idle cycles
180 Stats::Average<> notIdleFraction;
181 Stats::Formula idleFraction;
182
183 // number of cycles stalled for I-cache responses
184 Stats::Scalar<> icacheStallCycles;
185 Counter lastIcacheStall;
186
187 // number of cycles stalled for I-cache retries
188 Stats::Scalar<> icacheRetryCycles;
189 Counter lastIcacheRetry;
190
191 // number of cycles stalled for D-cache responses
192 Stats::Scalar<> dcacheStallCycles;
193 Counter lastDcacheStall;
194
195 // number of cycles stalled for D-cache retries
196 Stats::Scalar<> dcacheRetryCycles;
197 Counter lastDcacheRetry;
198
199 virtual void serialize(std::ostream &os);
200 virtual void unserialize(Checkpoint *cp, const std::string §ion);
201
202 // These functions are only used in CPU models that split
203 // effective address computation from the actual memory access.
204 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
205 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
206 M5_DUMMY_RETURN}
207
208 void prefetch(Addr addr, unsigned flags)
209 {
210 // need to do this...
211 }
212
213 void writeHint(Addr addr, int size, unsigned flags)
214 {
215 // need to do this...
216 }
217
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51namespace TheISA
52{
53 class ITB;
54 class DTB;
55}
56class MemObject;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63
64class RemoteGDB;
65class GDBListener;
66
67namespace TheISA
68{
69 class Predecoder;
70}
71class ThreadContext;
72class Checkpoint;
73
74namespace Trace {
75 class InstRecord;
76}
77
78
79class BaseSimpleCPU : public BaseCPU
80{
81 protected:
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::FloatReg FloatReg;
84 typedef TheISA::FloatRegBits FloatRegBits;
85
86 protected:
87 Trace::InstRecord *traceData;
88
89 public:
90 void post_interrupt(int int_num, int index);
91
92 void zero_fill_64(Addr addr) {
93 static int warned = 0;
94 if (!warned) {
95 warn ("WH64 is not implemented");
96 warned = 1;
97 }
98 };
99
100 public:
101 struct Params : public BaseCPU::Params
102 {
103#if FULL_SYSTEM
104 TheISA::ITB *itb;
105 TheISA::DTB *dtb;
106#else
107 Process *process;
108#endif
109 };
110 BaseSimpleCPU(Params *params);
111 virtual ~BaseSimpleCPU();
112
113 public:
114 /** SimpleThread object, provides all the architectural state. */
115 SimpleThread *thread;
116
117 /** ThreadContext object, provides an interface for external
118 * objects to modify this thread's state.
119 */
120 ThreadContext *tc;
121
122#if FULL_SYSTEM
123 Addr dbg_vtophys(Addr addr);
124
125 bool interval_stats;
126#endif
127
128 // current instruction
129 TheISA::MachInst inst;
130
131 // The predecoder
132 TheISA::Predecoder predecoder;
133
134 // Static data storage
135 TheISA::LargestRead dataReg;
136
137 StaticInstPtr curStaticInst;
138 StaticInstPtr curMacroStaticInst;
139
140 //This is the offset from the current pc that fetch should be performed at
141 Addr fetchOffset;
142 //This flag says to stay at the current pc. This is useful for
143 //instructions which go beyond MachInst boundaries.
144 bool stayAtPC;
145
146 void checkForInterrupts();
147 Fault setupFetchRequest(Request *req);
148 void preExecute();
149 void postExecute();
150 void advancePC(Fault fault);
151
152 virtual void deallocateContext(int thread_num);
153 virtual void haltContext(int thread_num);
154
155 // statistics
156 virtual void regStats();
157 virtual void resetStats();
158
159 // number of simulated instructions
160 Counter numInst;
161 Counter startNumInst;
162 Stats::Scalar<> numInsts;
163
164 virtual Counter totalInstructions() const
165 {
166 return numInst - startNumInst;
167 }
168
169 // Mask to align PCs to MachInst sized boundaries
170 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
171
172 // number of simulated memory references
173 Stats::Scalar<> numMemRefs;
174
175 // number of simulated loads
176 Counter numLoad;
177 Counter startNumLoad;
178
179 // number of idle cycles
180 Stats::Average<> notIdleFraction;
181 Stats::Formula idleFraction;
182
183 // number of cycles stalled for I-cache responses
184 Stats::Scalar<> icacheStallCycles;
185 Counter lastIcacheStall;
186
187 // number of cycles stalled for I-cache retries
188 Stats::Scalar<> icacheRetryCycles;
189 Counter lastIcacheRetry;
190
191 // number of cycles stalled for D-cache responses
192 Stats::Scalar<> dcacheStallCycles;
193 Counter lastDcacheStall;
194
195 // number of cycles stalled for D-cache retries
196 Stats::Scalar<> dcacheRetryCycles;
197 Counter lastDcacheRetry;
198
199 virtual void serialize(std::ostream &os);
200 virtual void unserialize(Checkpoint *cp, const std::string §ion);
201
202 // These functions are only used in CPU models that split
203 // effective address computation from the actual memory access.
204 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
205 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
206 M5_DUMMY_RETURN}
207
208 void prefetch(Addr addr, unsigned flags)
209 {
210 // need to do this...
211 }
212
213 void writeHint(Addr addr, int size, unsigned flags)
214 {
215 // need to do this...
216 }
217
|
218 Fault copySrcTranslate(Addr src);
219
220 Fault copy(Addr dest);
221
222 // The register accessor methods provide the index of the
223 // instruction's operand (e.g., 0 or 1), not the architectural
224 // register index, to simplify the implementation of register
225 // renaming. We find the architectural register index by indexing
226 // into the instruction's own operand index table. Note that a
227 // raw pointer to the StaticInst is provided instead of a
228 // ref-counted StaticInstPtr to redice overhead. This is fine as
229 // long as these methods don't copy the pointer into any long-term
230 // storage (which is pretty hard to imagine they would have reason
231 // to do).
232
233 uint64_t readIntRegOperand(const StaticInst *si, int idx)
234 {
235 return thread->readIntReg(si->srcRegIdx(idx));
236 }
237
238 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
239 {
240 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
241 return thread->readFloatReg(reg_idx, width);
242 }
243
244 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
245 {
246 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
247 return thread->readFloatReg(reg_idx);
248 }
249
250 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
251 int width)
252 {
253 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
254 return thread->readFloatRegBits(reg_idx, width);
255 }
256
257 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
258 {
259 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
260 return thread->readFloatRegBits(reg_idx);
261 }
262
263 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
264 {
265 thread->setIntReg(si->destRegIdx(idx), val);
266 }
267
268 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
269 int width)
270 {
271 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
272 thread->setFloatReg(reg_idx, val, width);
273 }
274
275 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
276 {
277 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
278 thread->setFloatReg(reg_idx, val);
279 }
280
281 void setFloatRegOperandBits(const StaticInst *si, int idx,
282 FloatRegBits val, int width)
283 {
284 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
285 thread->setFloatRegBits(reg_idx, val, width);
286 }
287
288 void setFloatRegOperandBits(const StaticInst *si, int idx,
289 FloatRegBits val)
290 {
291 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
292 thread->setFloatRegBits(reg_idx, val);
293 }
294
295 uint64_t readPC() { return thread->readPC(); }
296 uint64_t readNextPC() { return thread->readNextPC(); }
297 uint64_t readNextNPC() { return thread->readNextNPC(); }
298
299 void setPC(uint64_t val) { thread->setPC(val); }
300 void setNextPC(uint64_t val) { thread->setNextPC(val); }
301 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
302
303 MiscReg readMiscRegNoEffect(int misc_reg)
304 {
305 return thread->readMiscRegNoEffect(misc_reg);
306 }
307
308 MiscReg readMiscReg(int misc_reg)
309 {
310 return thread->readMiscReg(misc_reg);
311 }
312
313 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
314 {
315 return thread->setMiscRegNoEffect(misc_reg, val);
316 }
317
318 void setMiscReg(int misc_reg, const MiscReg &val)
319 {
320 return thread->setMiscReg(misc_reg, val);
321 }
322
323 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
324 {
325 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
326 return thread->readMiscRegNoEffect(reg_idx);
327 }
328
329 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
330 {
331 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
332 return thread->readMiscReg(reg_idx);
333 }
334
335 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
336 {
337 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
338 return thread->setMiscRegNoEffect(reg_idx, val);
339 }
340
341 void setMiscRegOperand(
342 const StaticInst *si, int idx, const MiscReg &val)
343 {
344 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
345 return thread->setMiscReg(reg_idx, val);
346 }
347
348 unsigned readStCondFailures() {
349 return thread->readStCondFailures();
350 }
351
352 void setStCondFailures(unsigned sc_failures) {
353 thread->setStCondFailures(sc_failures);
354 }
355
| 219 Fault copySrcTranslate(Addr src);
220
221 Fault copy(Addr dest);
222
223 // The register accessor methods provide the index of the
224 // instruction's operand (e.g., 0 or 1), not the architectural
225 // register index, to simplify the implementation of register
226 // renaming. We find the architectural register index by indexing
227 // into the instruction's own operand index table. Note that a
228 // raw pointer to the StaticInst is provided instead of a
229 // ref-counted StaticInstPtr to redice overhead. This is fine as
230 // long as these methods don't copy the pointer into any long-term
231 // storage (which is pretty hard to imagine they would have reason
232 // to do).
233
234 uint64_t readIntRegOperand(const StaticInst *si, int idx)
235 {
236 return thread->readIntReg(si->srcRegIdx(idx));
237 }
238
239 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
240 {
241 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
242 return thread->readFloatReg(reg_idx, width);
243 }
244
245 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
246 {
247 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
248 return thread->readFloatReg(reg_idx);
249 }
250
251 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
252 int width)
253 {
254 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
255 return thread->readFloatRegBits(reg_idx, width);
256 }
257
258 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
259 {
260 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
261 return thread->readFloatRegBits(reg_idx);
262 }
263
264 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
265 {
266 thread->setIntReg(si->destRegIdx(idx), val);
267 }
268
269 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
270 int width)
271 {
272 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
273 thread->setFloatReg(reg_idx, val, width);
274 }
275
276 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
277 {
278 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
279 thread->setFloatReg(reg_idx, val);
280 }
281
282 void setFloatRegOperandBits(const StaticInst *si, int idx,
283 FloatRegBits val, int width)
284 {
285 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
286 thread->setFloatRegBits(reg_idx, val, width);
287 }
288
289 void setFloatRegOperandBits(const StaticInst *si, int idx,
290 FloatRegBits val)
291 {
292 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
293 thread->setFloatRegBits(reg_idx, val);
294 }
295
296 uint64_t readPC() { return thread->readPC(); }
297 uint64_t readNextPC() { return thread->readNextPC(); }
298 uint64_t readNextNPC() { return thread->readNextNPC(); }
299
300 void setPC(uint64_t val) { thread->setPC(val); }
301 void setNextPC(uint64_t val) { thread->setNextPC(val); }
302 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
303
304 MiscReg readMiscRegNoEffect(int misc_reg)
305 {
306 return thread->readMiscRegNoEffect(misc_reg);
307 }
308
309 MiscReg readMiscReg(int misc_reg)
310 {
311 return thread->readMiscReg(misc_reg);
312 }
313
314 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
315 {
316 return thread->setMiscRegNoEffect(misc_reg, val);
317 }
318
319 void setMiscReg(int misc_reg, const MiscReg &val)
320 {
321 return thread->setMiscReg(misc_reg, val);
322 }
323
324 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
325 {
326 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
327 return thread->readMiscRegNoEffect(reg_idx);
328 }
329
330 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
331 {
332 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
333 return thread->readMiscReg(reg_idx);
334 }
335
336 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
337 {
338 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
339 return thread->setMiscRegNoEffect(reg_idx, val);
340 }
341
342 void setMiscRegOperand(
343 const StaticInst *si, int idx, const MiscReg &val)
344 {
345 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
346 return thread->setMiscReg(reg_idx, val);
347 }
348
349 unsigned readStCondFailures() {
350 return thread->readStCondFailures();
351 }
352
353 void setStCondFailures(unsigned sc_failures) {
354 thread->setStCondFailures(sc_failures);
355 }
356
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