base.hh (3276:dc3cd126b479) base.hh (3402:db60546818d0)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "base/statistics.hh"
37#include "config/full_system.hh"
38#include "cpu/base.hh"
39#include "cpu/simple_thread.hh"
40#include "cpu/pc_event.hh"
41#include "cpu/static_inst.hh"
42#include "mem/packet.hh"
43#include "mem/port.hh"
44#include "mem/request.hh"
45#include "sim/eventq.hh"
46
47// forward declarations
48#if FULL_SYSTEM
49class Processor;
50class AlphaITB;
51class AlphaDTB;
52class MemObject;
53
54class RemoteGDB;
55class GDBListener;
56
57#else
58
59class Process;
60
61#endif // FULL_SYSTEM
62
63class ThreadContext;
64class Checkpoint;
65
66namespace Trace {
67 class InstRecord;
68}
69
70
71class BaseSimpleCPU : public BaseCPU
72{
73 protected:
74 typedef TheISA::MachInst MachInst;
75 typedef TheISA::MiscReg MiscReg;
76 typedef TheISA::FloatReg FloatReg;
77 typedef TheISA::FloatRegBits FloatRegBits;
78
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "base/statistics.hh"
37#include "config/full_system.hh"
38#include "cpu/base.hh"
39#include "cpu/simple_thread.hh"
40#include "cpu/pc_event.hh"
41#include "cpu/static_inst.hh"
42#include "mem/packet.hh"
43#include "mem/port.hh"
44#include "mem/request.hh"
45#include "sim/eventq.hh"
46
47// forward declarations
48#if FULL_SYSTEM
49class Processor;
50class AlphaITB;
51class AlphaDTB;
52class MemObject;
53
54class RemoteGDB;
55class GDBListener;
56
57#else
58
59class Process;
60
61#endif // FULL_SYSTEM
62
63class ThreadContext;
64class Checkpoint;
65
66namespace Trace {
67 class InstRecord;
68}
69
70
71class BaseSimpleCPU : public BaseCPU
72{
73 protected:
74 typedef TheISA::MachInst MachInst;
75 typedef TheISA::MiscReg MiscReg;
76 typedef TheISA::FloatReg FloatReg;
77 typedef TheISA::FloatRegBits FloatRegBits;
78
79 MemObject *mem;
80
81 protected:
82 Trace::InstRecord *traceData;
83
84 public:
85 void post_interrupt(int int_num, int index);
86
87 void zero_fill_64(Addr addr) {
88 static int warned = 0;
89 if (!warned) {
90 warn ("WH64 is not implemented");
91 warned = 1;
92 }
93 };
94
95 public:
96 struct Params : public BaseCPU::Params
97 {
79 protected:
80 Trace::InstRecord *traceData;
81
82 public:
83 void post_interrupt(int int_num, int index);
84
85 void zero_fill_64(Addr addr) {
86 static int warned = 0;
87 if (!warned) {
88 warn ("WH64 is not implemented");
89 warned = 1;
90 }
91 };
92
93 public:
94 struct Params : public BaseCPU::Params
95 {
98 MemObject *mem;
99#if FULL_SYSTEM
100 AlphaITB *itb;
101 AlphaDTB *dtb;
102#else
103 Process *process;
104#endif
105 };
106 BaseSimpleCPU(Params *params);
107 virtual ~BaseSimpleCPU();
108
109 public:
110 /** SimpleThread object, provides all the architectural state. */
111 SimpleThread *thread;
112
113 /** ThreadContext object, provides an interface for external
114 * objects to modify this thread's state.
115 */
116 ThreadContext *tc;
117
118#if FULL_SYSTEM
119 Addr dbg_vtophys(Addr addr);
120
121 bool interval_stats;
122#endif
123
124 // current instruction
125 MachInst inst;
126
127 // Static data storage
128 TheISA::IntReg dataReg;
129
130 StaticInstPtr curStaticInst;
131 StaticInstPtr curMacroStaticInst;
132
133 void checkForInterrupts();
134 Fault setupFetchRequest(Request *req);
135 void preExecute();
136 void postExecute();
137 void advancePC(Fault fault);
138
139 virtual void deallocateContext(int thread_num);
140 virtual void haltContext(int thread_num);
141
142 // statistics
143 virtual void regStats();
144 virtual void resetStats();
145
146 // number of simulated instructions
147 Counter numInst;
148 Counter startNumInst;
149 Stats::Scalar<> numInsts;
150
151 virtual Counter totalInstructions() const
152 {
153 return numInst - startNumInst;
154 }
155
156 // number of simulated memory references
157 Stats::Scalar<> numMemRefs;
158
159 // number of simulated loads
160 Counter numLoad;
161 Counter startNumLoad;
162
163 // number of idle cycles
164 Stats::Average<> notIdleFraction;
165 Stats::Formula idleFraction;
166
167 // number of cycles stalled for I-cache responses
168 Stats::Scalar<> icacheStallCycles;
169 Counter lastIcacheStall;
170
171 // number of cycles stalled for I-cache retries
172 Stats::Scalar<> icacheRetryCycles;
173 Counter lastIcacheRetry;
174
175 // number of cycles stalled for D-cache responses
176 Stats::Scalar<> dcacheStallCycles;
177 Counter lastDcacheStall;
178
179 // number of cycles stalled for D-cache retries
180 Stats::Scalar<> dcacheRetryCycles;
181 Counter lastDcacheRetry;
182
183 virtual void serialize(std::ostream &os);
184 virtual void unserialize(Checkpoint *cp, const std::string &section);
185
186 // These functions are only used in CPU models that split
187 // effective address computation from the actual memory access.
188 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
189 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); }
190
191 void prefetch(Addr addr, unsigned flags)
192 {
193 // need to do this...
194 }
195
196 void writeHint(Addr addr, int size, unsigned flags)
197 {
198 // need to do this...
199 }
200
201 Fault copySrcTranslate(Addr src);
202
203 Fault copy(Addr dest);
204
205 // The register accessor methods provide the index of the
206 // instruction's operand (e.g., 0 or 1), not the architectural
207 // register index, to simplify the implementation of register
208 // renaming. We find the architectural register index by indexing
209 // into the instruction's own operand index table. Note that a
210 // raw pointer to the StaticInst is provided instead of a
211 // ref-counted StaticInstPtr to redice overhead. This is fine as
212 // long as these methods don't copy the pointer into any long-term
213 // storage (which is pretty hard to imagine they would have reason
214 // to do).
215
216 uint64_t readIntReg(const StaticInst *si, int idx)
217 {
218 return thread->readIntReg(si->srcRegIdx(idx));
219 }
220
221 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
222 {
223 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
224 return thread->readFloatReg(reg_idx, width);
225 }
226
227 FloatReg readFloatReg(const StaticInst *si, int idx)
228 {
229 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
230 return thread->readFloatReg(reg_idx);
231 }
232
233 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
234 {
235 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
236 return thread->readFloatRegBits(reg_idx, width);
237 }
238
239 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
240 {
241 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
242 return thread->readFloatRegBits(reg_idx);
243 }
244
245 void setIntReg(const StaticInst *si, int idx, uint64_t val)
246 {
247 thread->setIntReg(si->destRegIdx(idx), val);
248 }
249
250 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
251 {
252 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
253 thread->setFloatReg(reg_idx, val, width);
254 }
255
256 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
257 {
258 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
259 thread->setFloatReg(reg_idx, val);
260 }
261
262 void setFloatRegBits(const StaticInst *si, int idx,
263 FloatRegBits val, int width)
264 {
265 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
266 thread->setFloatRegBits(reg_idx, val, width);
267 }
268
269 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
270 {
271 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
272 thread->setFloatRegBits(reg_idx, val);
273 }
274
275 uint64_t readPC() { return thread->readPC(); }
276 uint64_t readNextPC() { return thread->readNextPC(); }
277 uint64_t readNextNPC() { return thread->readNextNPC(); }
278
279 void setPC(uint64_t val) { thread->setPC(val); }
280 void setNextPC(uint64_t val) { thread->setNextPC(val); }
281 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
282
283 MiscReg readMiscReg(int misc_reg)
284 {
285 return thread->readMiscReg(misc_reg);
286 }
287
288 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
289 {
290 return thread->readMiscRegWithEffect(misc_reg, fault);
291 }
292
293 Fault setMiscReg(int misc_reg, const MiscReg &val)
294 {
295 return thread->setMiscReg(misc_reg, val);
296 }
297
298 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
299 {
300 return thread->setMiscRegWithEffect(misc_reg, val);
301 }
302
303#if FULL_SYSTEM
304 Fault hwrei() { return thread->hwrei(); }
305 int readIntrFlag() { return thread->readIntrFlag(); }
306 void setIntrFlag(int val) { thread->setIntrFlag(val); }
307 bool inPalMode() { return thread->inPalMode(); }
308 void ev5_trap(Fault fault) { fault->invoke(tc); }
309 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
310#else
311 void syscall(int64_t callnum) { thread->syscall(callnum); }
312#endif
313
314 bool misspeculating() { return thread->misspeculating(); }
315 ThreadContext *tcBase() { return tc; }
316};
317
318#endif // __CPU_SIMPLE_BASE_HH__
96#if FULL_SYSTEM
97 AlphaITB *itb;
98 AlphaDTB *dtb;
99#else
100 Process *process;
101#endif
102 };
103 BaseSimpleCPU(Params *params);
104 virtual ~BaseSimpleCPU();
105
106 public:
107 /** SimpleThread object, provides all the architectural state. */
108 SimpleThread *thread;
109
110 /** ThreadContext object, provides an interface for external
111 * objects to modify this thread's state.
112 */
113 ThreadContext *tc;
114
115#if FULL_SYSTEM
116 Addr dbg_vtophys(Addr addr);
117
118 bool interval_stats;
119#endif
120
121 // current instruction
122 MachInst inst;
123
124 // Static data storage
125 TheISA::IntReg dataReg;
126
127 StaticInstPtr curStaticInst;
128 StaticInstPtr curMacroStaticInst;
129
130 void checkForInterrupts();
131 Fault setupFetchRequest(Request *req);
132 void preExecute();
133 void postExecute();
134 void advancePC(Fault fault);
135
136 virtual void deallocateContext(int thread_num);
137 virtual void haltContext(int thread_num);
138
139 // statistics
140 virtual void regStats();
141 virtual void resetStats();
142
143 // number of simulated instructions
144 Counter numInst;
145 Counter startNumInst;
146 Stats::Scalar<> numInsts;
147
148 virtual Counter totalInstructions() const
149 {
150 return numInst - startNumInst;
151 }
152
153 // number of simulated memory references
154 Stats::Scalar<> numMemRefs;
155
156 // number of simulated loads
157 Counter numLoad;
158 Counter startNumLoad;
159
160 // number of idle cycles
161 Stats::Average<> notIdleFraction;
162 Stats::Formula idleFraction;
163
164 // number of cycles stalled for I-cache responses
165 Stats::Scalar<> icacheStallCycles;
166 Counter lastIcacheStall;
167
168 // number of cycles stalled for I-cache retries
169 Stats::Scalar<> icacheRetryCycles;
170 Counter lastIcacheRetry;
171
172 // number of cycles stalled for D-cache responses
173 Stats::Scalar<> dcacheStallCycles;
174 Counter lastDcacheStall;
175
176 // number of cycles stalled for D-cache retries
177 Stats::Scalar<> dcacheRetryCycles;
178 Counter lastDcacheRetry;
179
180 virtual void serialize(std::ostream &os);
181 virtual void unserialize(Checkpoint *cp, const std::string &section);
182
183 // These functions are only used in CPU models that split
184 // effective address computation from the actual memory access.
185 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
186 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); }
187
188 void prefetch(Addr addr, unsigned flags)
189 {
190 // need to do this...
191 }
192
193 void writeHint(Addr addr, int size, unsigned flags)
194 {
195 // need to do this...
196 }
197
198 Fault copySrcTranslate(Addr src);
199
200 Fault copy(Addr dest);
201
202 // The register accessor methods provide the index of the
203 // instruction's operand (e.g., 0 or 1), not the architectural
204 // register index, to simplify the implementation of register
205 // renaming. We find the architectural register index by indexing
206 // into the instruction's own operand index table. Note that a
207 // raw pointer to the StaticInst is provided instead of a
208 // ref-counted StaticInstPtr to redice overhead. This is fine as
209 // long as these methods don't copy the pointer into any long-term
210 // storage (which is pretty hard to imagine they would have reason
211 // to do).
212
213 uint64_t readIntReg(const StaticInst *si, int idx)
214 {
215 return thread->readIntReg(si->srcRegIdx(idx));
216 }
217
218 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
219 {
220 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
221 return thread->readFloatReg(reg_idx, width);
222 }
223
224 FloatReg readFloatReg(const StaticInst *si, int idx)
225 {
226 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
227 return thread->readFloatReg(reg_idx);
228 }
229
230 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
231 {
232 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
233 return thread->readFloatRegBits(reg_idx, width);
234 }
235
236 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
237 {
238 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
239 return thread->readFloatRegBits(reg_idx);
240 }
241
242 void setIntReg(const StaticInst *si, int idx, uint64_t val)
243 {
244 thread->setIntReg(si->destRegIdx(idx), val);
245 }
246
247 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
248 {
249 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
250 thread->setFloatReg(reg_idx, val, width);
251 }
252
253 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
254 {
255 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
256 thread->setFloatReg(reg_idx, val);
257 }
258
259 void setFloatRegBits(const StaticInst *si, int idx,
260 FloatRegBits val, int width)
261 {
262 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
263 thread->setFloatRegBits(reg_idx, val, width);
264 }
265
266 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
267 {
268 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
269 thread->setFloatRegBits(reg_idx, val);
270 }
271
272 uint64_t readPC() { return thread->readPC(); }
273 uint64_t readNextPC() { return thread->readNextPC(); }
274 uint64_t readNextNPC() { return thread->readNextNPC(); }
275
276 void setPC(uint64_t val) { thread->setPC(val); }
277 void setNextPC(uint64_t val) { thread->setNextPC(val); }
278 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
279
280 MiscReg readMiscReg(int misc_reg)
281 {
282 return thread->readMiscReg(misc_reg);
283 }
284
285 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
286 {
287 return thread->readMiscRegWithEffect(misc_reg, fault);
288 }
289
290 Fault setMiscReg(int misc_reg, const MiscReg &val)
291 {
292 return thread->setMiscReg(misc_reg, val);
293 }
294
295 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
296 {
297 return thread->setMiscRegWithEffect(misc_reg, val);
298 }
299
300#if FULL_SYSTEM
301 Fault hwrei() { return thread->hwrei(); }
302 int readIntrFlag() { return thread->readIntrFlag(); }
303 void setIntrFlag(int val) { thread->setIntrFlag(val); }
304 bool inPalMode() { return thread->inPalMode(); }
305 void ev5_trap(Fault fault) { fault->invoke(tc); }
306 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
307#else
308 void syscall(int64_t callnum) { thread->syscall(callnum); }
309#endif
310
311 bool misspeculating() { return thread->misspeculating(); }
312 ThreadContext *tcBase() { return tc; }
313};
314
315#endif // __CPU_SIMPLE_BASE_HH__