1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "base/statistics.hh"
37#include "config/full_system.hh"
38#include "cpu/base.hh"
39#include "cpu/simple_thread.hh"
40#include "cpu/pc_event.hh"
41#include "cpu/static_inst.hh"
42#include "mem/packet.hh"
43#include "mem/port.hh"
44#include "mem/request.hh"
45#include "sim/eventq.hh"
46
47// forward declarations
48#if FULL_SYSTEM
49class Processor;
50class AlphaITB;
51class AlphaDTB;
52class MemObject;
53
54class RemoteGDB;
55class GDBListener;
56
57#else
58
59class Process;
60
61#endif // FULL_SYSTEM
62
63class ThreadContext;
64class Checkpoint;
65
66namespace Trace {
67 class InstRecord;
68}
69
70
71class BaseSimpleCPU : public BaseCPU
72{
73 protected:
74 typedef TheISA::MachInst MachInst;
75 typedef TheISA::MiscReg MiscReg;
76 typedef TheISA::FloatReg FloatReg;
77 typedef TheISA::FloatRegBits FloatRegBits;
78
79 MemObject *mem;
80
81 protected:
82 Trace::InstRecord *traceData;
83
84 public:
85 void post_interrupt(int int_num, int index);
86
87 void zero_fill_64(Addr addr) {
88 static int warned = 0;
89 if (!warned) {
90 warn ("WH64 is not implemented");
91 warned = 1;
92 }
93 };
94
95 public:
96 struct Params : public BaseCPU::Params
97 {
98 MemObject *mem;
99#if FULL_SYSTEM
100 AlphaITB *itb;
101 AlphaDTB *dtb;
102#else
103 Process *process;
104#endif
105 };
106 BaseSimpleCPU(Params *params);
107 virtual ~BaseSimpleCPU();
108
109 public:
110 /** SimpleThread object, provides all the architectural state. */
111 SimpleThread *thread;
112
113 /** ThreadContext object, provides an interface for external
114 * objects to modify this thread's state.
115 */
116 ThreadContext *tc;
117
118#if FULL_SYSTEM
119 Addr dbg_vtophys(Addr addr);
120
121 bool interval_stats;
122#endif
123
124 // current instruction
125 MachInst inst;
126
127 // Static data storage
128 TheISA::IntReg dataReg;
129
130 StaticInstPtr curStaticInst;
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "base/statistics.hh"
37#include "config/full_system.hh"
38#include "cpu/base.hh"
39#include "cpu/simple_thread.hh"
40#include "cpu/pc_event.hh"
41#include "cpu/static_inst.hh"
42#include "mem/packet.hh"
43#include "mem/port.hh"
44#include "mem/request.hh"
45#include "sim/eventq.hh"
46
47// forward declarations
48#if FULL_SYSTEM
49class Processor;
50class AlphaITB;
51class AlphaDTB;
52class MemObject;
53
54class RemoteGDB;
55class GDBListener;
56
57#else
58
59class Process;
60
61#endif // FULL_SYSTEM
62
63class ThreadContext;
64class Checkpoint;
65
66namespace Trace {
67 class InstRecord;
68}
69
70
71class BaseSimpleCPU : public BaseCPU
72{
73 protected:
74 typedef TheISA::MachInst MachInst;
75 typedef TheISA::MiscReg MiscReg;
76 typedef TheISA::FloatReg FloatReg;
77 typedef TheISA::FloatRegBits FloatRegBits;
78
79 MemObject *mem;
80
81 protected:
82 Trace::InstRecord *traceData;
83
84 public:
85 void post_interrupt(int int_num, int index);
86
87 void zero_fill_64(Addr addr) {
88 static int warned = 0;
89 if (!warned) {
90 warn ("WH64 is not implemented");
91 warned = 1;
92 }
93 };
94
95 public:
96 struct Params : public BaseCPU::Params
97 {
98 MemObject *mem;
99#if FULL_SYSTEM
100 AlphaITB *itb;
101 AlphaDTB *dtb;
102#else
103 Process *process;
104#endif
105 };
106 BaseSimpleCPU(Params *params);
107 virtual ~BaseSimpleCPU();
108
109 public:
110 /** SimpleThread object, provides all the architectural state. */
111 SimpleThread *thread;
112
113 /** ThreadContext object, provides an interface for external
114 * objects to modify this thread's state.
115 */
116 ThreadContext *tc;
117
118#if FULL_SYSTEM
119 Addr dbg_vtophys(Addr addr);
120
121 bool interval_stats;
122#endif
123
124 // current instruction
125 MachInst inst;
126
127 // Static data storage
128 TheISA::IntReg dataReg;
129
130 StaticInstPtr curStaticInst;
|
131
132 void checkForInterrupts();
133 Fault setupFetchRequest(Request *req);
134 void preExecute();
135 void postExecute();
136 void advancePC(Fault fault);
137
138 virtual void deallocateContext(int thread_num);
139 virtual void haltContext(int thread_num);
140
141 // statistics
142 virtual void regStats();
143 virtual void resetStats();
144
145 // number of simulated instructions
146 Counter numInst;
147 Counter startNumInst;
148 Stats::Scalar<> numInsts;
149
150 virtual Counter totalInstructions() const
151 {
152 return numInst - startNumInst;
153 }
154
155 // number of simulated memory references
156 Stats::Scalar<> numMemRefs;
157
158 // number of simulated loads
159 Counter numLoad;
160 Counter startNumLoad;
161
162 // number of idle cycles
163 Stats::Average<> notIdleFraction;
164 Stats::Formula idleFraction;
165
166 // number of cycles stalled for I-cache responses
167 Stats::Scalar<> icacheStallCycles;
168 Counter lastIcacheStall;
169
170 // number of cycles stalled for I-cache retries
171 Stats::Scalar<> icacheRetryCycles;
172 Counter lastIcacheRetry;
173
174 // number of cycles stalled for D-cache responses
175 Stats::Scalar<> dcacheStallCycles;
176 Counter lastDcacheStall;
177
178 // number of cycles stalled for D-cache retries
179 Stats::Scalar<> dcacheRetryCycles;
180 Counter lastDcacheRetry;
181
182 virtual void serialize(std::ostream &os);
183 virtual void unserialize(Checkpoint *cp, const std::string §ion);
184
185 // These functions are only used in CPU models that split
186 // effective address computation from the actual memory access.
187 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
188 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); }
189
190 void prefetch(Addr addr, unsigned flags)
191 {
192 // need to do this...
193 }
194
195 void writeHint(Addr addr, int size, unsigned flags)
196 {
197 // need to do this...
198 }
199
200 Fault copySrcTranslate(Addr src);
201
202 Fault copy(Addr dest);
203
204 // The register accessor methods provide the index of the
205 // instruction's operand (e.g., 0 or 1), not the architectural
206 // register index, to simplify the implementation of register
207 // renaming. We find the architectural register index by indexing
208 // into the instruction's own operand index table. Note that a
209 // raw pointer to the StaticInst is provided instead of a
210 // ref-counted StaticInstPtr to redice overhead. This is fine as
211 // long as these methods don't copy the pointer into any long-term
212 // storage (which is pretty hard to imagine they would have reason
213 // to do).
214
215 uint64_t readIntReg(const StaticInst *si, int idx)
216 {
217 return thread->readIntReg(si->srcRegIdx(idx));
218 }
219
220 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
221 {
222 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
223 return thread->readFloatReg(reg_idx, width);
224 }
225
226 FloatReg readFloatReg(const StaticInst *si, int idx)
227 {
228 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
229 return thread->readFloatReg(reg_idx);
230 }
231
232 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
233 {
234 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
235 return thread->readFloatRegBits(reg_idx, width);
236 }
237
238 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
239 {
240 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
241 return thread->readFloatRegBits(reg_idx);
242 }
243
244 void setIntReg(const StaticInst *si, int idx, uint64_t val)
245 {
246 thread->setIntReg(si->destRegIdx(idx), val);
247 }
248
249 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
250 {
251 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
252 thread->setFloatReg(reg_idx, val, width);
253 }
254
255 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
256 {
257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
258 thread->setFloatReg(reg_idx, val);
259 }
260
261 void setFloatRegBits(const StaticInst *si, int idx,
262 FloatRegBits val, int width)
263 {
264 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
265 thread->setFloatRegBits(reg_idx, val, width);
266 }
267
268 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
269 {
270 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
271 thread->setFloatRegBits(reg_idx, val);
272 }
273
274 uint64_t readPC() { return thread->readPC(); }
275 uint64_t readNextPC() { return thread->readNextPC(); }
276 uint64_t readNextNPC() { return thread->readNextNPC(); }
277
278 void setPC(uint64_t val) { thread->setPC(val); }
279 void setNextPC(uint64_t val) { thread->setNextPC(val); }
280 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
281
282 MiscReg readMiscReg(int misc_reg)
283 {
284 return thread->readMiscReg(misc_reg);
285 }
286
287 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
288 {
289 return thread->readMiscRegWithEffect(misc_reg, fault);
290 }
291
292 Fault setMiscReg(int misc_reg, const MiscReg &val)
293 {
294 return thread->setMiscReg(misc_reg, val);
295 }
296
297 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
298 {
299 return thread->setMiscRegWithEffect(misc_reg, val);
300 }
301
302#if FULL_SYSTEM
303 Fault hwrei() { return thread->hwrei(); }
304 int readIntrFlag() { return thread->readIntrFlag(); }
305 void setIntrFlag(int val) { thread->setIntrFlag(val); }
306 bool inPalMode() { return thread->inPalMode(); }
307 void ev5_trap(Fault fault) { fault->invoke(tc); }
308 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
309#else
310 void syscall(int64_t callnum) { thread->syscall(callnum); }
311#endif
312
313 bool misspeculating() { return thread->misspeculating(); }
314 ThreadContext *tcBase() { return tc; }
315};
316
317#endif // __CPU_SIMPLE_BASE_HH__
| 132
133 void checkForInterrupts();
134 Fault setupFetchRequest(Request *req);
135 void preExecute();
136 void postExecute();
137 void advancePC(Fault fault);
138
139 virtual void deallocateContext(int thread_num);
140 virtual void haltContext(int thread_num);
141
142 // statistics
143 virtual void regStats();
144 virtual void resetStats();
145
146 // number of simulated instructions
147 Counter numInst;
148 Counter startNumInst;
149 Stats::Scalar<> numInsts;
150
151 virtual Counter totalInstructions() const
152 {
153 return numInst - startNumInst;
154 }
155
156 // number of simulated memory references
157 Stats::Scalar<> numMemRefs;
158
159 // number of simulated loads
160 Counter numLoad;
161 Counter startNumLoad;
162
163 // number of idle cycles
164 Stats::Average<> notIdleFraction;
165 Stats::Formula idleFraction;
166
167 // number of cycles stalled for I-cache responses
168 Stats::Scalar<> icacheStallCycles;
169 Counter lastIcacheStall;
170
171 // number of cycles stalled for I-cache retries
172 Stats::Scalar<> icacheRetryCycles;
173 Counter lastIcacheRetry;
174
175 // number of cycles stalled for D-cache responses
176 Stats::Scalar<> dcacheStallCycles;
177 Counter lastDcacheStall;
178
179 // number of cycles stalled for D-cache retries
180 Stats::Scalar<> dcacheRetryCycles;
181 Counter lastDcacheRetry;
182
183 virtual void serialize(std::ostream &os);
184 virtual void unserialize(Checkpoint *cp, const std::string §ion);
185
186 // These functions are only used in CPU models that split
187 // effective address computation from the actual memory access.
188 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
189 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); }
190
191 void prefetch(Addr addr, unsigned flags)
192 {
193 // need to do this...
194 }
195
196 void writeHint(Addr addr, int size, unsigned flags)
197 {
198 // need to do this...
199 }
200
201 Fault copySrcTranslate(Addr src);
202
203 Fault copy(Addr dest);
204
205 // The register accessor methods provide the index of the
206 // instruction's operand (e.g., 0 or 1), not the architectural
207 // register index, to simplify the implementation of register
208 // renaming. We find the architectural register index by indexing
209 // into the instruction's own operand index table. Note that a
210 // raw pointer to the StaticInst is provided instead of a
211 // ref-counted StaticInstPtr to redice overhead. This is fine as
212 // long as these methods don't copy the pointer into any long-term
213 // storage (which is pretty hard to imagine they would have reason
214 // to do).
215
216 uint64_t readIntReg(const StaticInst *si, int idx)
217 {
218 return thread->readIntReg(si->srcRegIdx(idx));
219 }
220
221 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
222 {
223 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
224 return thread->readFloatReg(reg_idx, width);
225 }
226
227 FloatReg readFloatReg(const StaticInst *si, int idx)
228 {
229 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
230 return thread->readFloatReg(reg_idx);
231 }
232
233 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
234 {
235 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
236 return thread->readFloatRegBits(reg_idx, width);
237 }
238
239 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
240 {
241 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
242 return thread->readFloatRegBits(reg_idx);
243 }
244
245 void setIntReg(const StaticInst *si, int idx, uint64_t val)
246 {
247 thread->setIntReg(si->destRegIdx(idx), val);
248 }
249
250 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
251 {
252 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
253 thread->setFloatReg(reg_idx, val, width);
254 }
255
256 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
257 {
258 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
259 thread->setFloatReg(reg_idx, val);
260 }
261
262 void setFloatRegBits(const StaticInst *si, int idx,
263 FloatRegBits val, int width)
264 {
265 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
266 thread->setFloatRegBits(reg_idx, val, width);
267 }
268
269 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
270 {
271 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
272 thread->setFloatRegBits(reg_idx, val);
273 }
274
275 uint64_t readPC() { return thread->readPC(); }
276 uint64_t readNextPC() { return thread->readNextPC(); }
277 uint64_t readNextNPC() { return thread->readNextNPC(); }
278
279 void setPC(uint64_t val) { thread->setPC(val); }
280 void setNextPC(uint64_t val) { thread->setNextPC(val); }
281 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
282
283 MiscReg readMiscReg(int misc_reg)
284 {
285 return thread->readMiscReg(misc_reg);
286 }
287
288 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
289 {
290 return thread->readMiscRegWithEffect(misc_reg, fault);
291 }
292
293 Fault setMiscReg(int misc_reg, const MiscReg &val)
294 {
295 return thread->setMiscReg(misc_reg, val);
296 }
297
298 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
299 {
300 return thread->setMiscRegWithEffect(misc_reg, val);
301 }
302
303#if FULL_SYSTEM
304 Fault hwrei() { return thread->hwrei(); }
305 int readIntrFlag() { return thread->readIntrFlag(); }
306 void setIntrFlag(int val) { thread->setIntrFlag(val); }
307 bool inPalMode() { return thread->inPalMode(); }
308 void ev5_trap(Fault fault) { fault->invoke(tc); }
309 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
310#else
311 void syscall(int64_t callnum) { thread->syscall(callnum); }
312#endif
313
314 bool misspeculating() { return thread->misspeculating(); }
315 ThreadContext *tcBase() { return tc; }
316};
317
318#endif // __CPU_SIMPLE_BASE_HH__
|