base.hh (2683:d6b72bb2ed97) | base.hh (2840:227f7c4f8c81) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Dave Greene 30 * Nathan Binkert 31 */ 32 33#ifndef __CPU_SIMPLE_BASE_HH__ 34#define __CPU_SIMPLE_BASE_HH__ 35 36#include "base/statistics.hh" 37#include "config/full_system.hh" 38#include "cpu/base.hh" 39#include "cpu/simple_thread.hh" 40#include "cpu/pc_event.hh" | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Dave Greene 30 * Nathan Binkert 31 */ 32 33#ifndef __CPU_SIMPLE_BASE_HH__ 34#define __CPU_SIMPLE_BASE_HH__ 35 36#include "base/statistics.hh" 37#include "config/full_system.hh" 38#include "cpu/base.hh" 39#include "cpu/simple_thread.hh" 40#include "cpu/pc_event.hh" |
41#include "cpu/sampler/sampler.hh" | |
42#include "cpu/static_inst.hh" 43#include "mem/packet.hh" 44#include "mem/port.hh" 45#include "mem/request.hh" 46#include "sim/eventq.hh" 47 48// forward declarations 49#if FULL_SYSTEM 50class Processor; 51class AlphaITB; 52class AlphaDTB; 53class MemObject; 54 55class RemoteGDB; 56class GDBListener; 57 58#else 59 60class Process; 61 62#endif // FULL_SYSTEM 63 64class ThreadContext; 65class Checkpoint; 66 67namespace Trace { 68 class InstRecord; 69} 70 71 72class BaseSimpleCPU : public BaseCPU 73{ 74 protected: 75 typedef TheISA::MachInst MachInst; 76 typedef TheISA::MiscReg MiscReg; 77 typedef TheISA::FloatReg FloatReg; 78 typedef TheISA::FloatRegBits FloatRegBits; 79 80 MemObject *mem; 81 82 protected: 83 Trace::InstRecord *traceData; 84 85 public: 86 void post_interrupt(int int_num, int index); 87 88 void zero_fill_64(Addr addr) { 89 static int warned = 0; 90 if (!warned) { 91 warn ("WH64 is not implemented"); 92 warned = 1; 93 } 94 }; 95 96 public: 97 struct Params : public BaseCPU::Params 98 { 99 MemObject *mem; 100#if FULL_SYSTEM 101 AlphaITB *itb; 102 AlphaDTB *dtb; 103#else 104 Process *process; 105#endif 106 }; 107 BaseSimpleCPU(Params *params); 108 virtual ~BaseSimpleCPU(); 109 110 public: 111 /** SimpleThread object, provides all the architectural state. */ 112 SimpleThread *thread; 113 114 /** ThreadContext object, provides an interface for external 115 * objects to modify this thread's state. 116 */ 117 ThreadContext *tc; 118 119#if FULL_SYSTEM 120 Addr dbg_vtophys(Addr addr); 121 122 bool interval_stats; 123#endif 124 125 // current instruction 126 MachInst inst; 127 128 // Static data storage 129 TheISA::IntReg dataReg; 130 | 41#include "cpu/static_inst.hh" 42#include "mem/packet.hh" 43#include "mem/port.hh" 44#include "mem/request.hh" 45#include "sim/eventq.hh" 46 47// forward declarations 48#if FULL_SYSTEM 49class Processor; 50class AlphaITB; 51class AlphaDTB; 52class MemObject; 53 54class RemoteGDB; 55class GDBListener; 56 57#else 58 59class Process; 60 61#endif // FULL_SYSTEM 62 63class ThreadContext; 64class Checkpoint; 65 66namespace Trace { 67 class InstRecord; 68} 69 70 71class BaseSimpleCPU : public BaseCPU 72{ 73 protected: 74 typedef TheISA::MachInst MachInst; 75 typedef TheISA::MiscReg MiscReg; 76 typedef TheISA::FloatReg FloatReg; 77 typedef TheISA::FloatRegBits FloatRegBits; 78 79 MemObject *mem; 80 81 protected: 82 Trace::InstRecord *traceData; 83 84 public: 85 void post_interrupt(int int_num, int index); 86 87 void zero_fill_64(Addr addr) { 88 static int warned = 0; 89 if (!warned) { 90 warn ("WH64 is not implemented"); 91 warned = 1; 92 } 93 }; 94 95 public: 96 struct Params : public BaseCPU::Params 97 { 98 MemObject *mem; 99#if FULL_SYSTEM 100 AlphaITB *itb; 101 AlphaDTB *dtb; 102#else 103 Process *process; 104#endif 105 }; 106 BaseSimpleCPU(Params *params); 107 virtual ~BaseSimpleCPU(); 108 109 public: 110 /** SimpleThread object, provides all the architectural state. */ 111 SimpleThread *thread; 112 113 /** ThreadContext object, provides an interface for external 114 * objects to modify this thread's state. 115 */ 116 ThreadContext *tc; 117 118#if FULL_SYSTEM 119 Addr dbg_vtophys(Addr addr); 120 121 bool interval_stats; 122#endif 123 124 // current instruction 125 MachInst inst; 126 127 // Static data storage 128 TheISA::IntReg dataReg; 129 |
131 // Pointer to the sampler that is telling us to switchover. 132 // Used to signal the completion of the pipe drain and schedule 133 // the next switchover 134 Sampler *sampler; 135 | |
136 StaticInstPtr curStaticInst; 137 138 void checkForInterrupts(); 139 Fault setupFetchRequest(Request *req); 140 void preExecute(); 141 void postExecute(); 142 void advancePC(Fault fault); 143 144 virtual void deallocateContext(int thread_num); 145 virtual void haltContext(int thread_num); 146 147 // statistics 148 virtual void regStats(); 149 virtual void resetStats(); 150 151 // number of simulated instructions 152 Counter numInst; 153 Counter startNumInst; 154 Stats::Scalar<> numInsts; 155 156 virtual Counter totalInstructions() const 157 { 158 return numInst - startNumInst; 159 } 160 161 // number of simulated memory references 162 Stats::Scalar<> numMemRefs; 163 164 // number of simulated loads 165 Counter numLoad; 166 Counter startNumLoad; 167 168 // number of idle cycles 169 Stats::Average<> notIdleFraction; 170 Stats::Formula idleFraction; 171 172 // number of cycles stalled for I-cache responses 173 Stats::Scalar<> icacheStallCycles; 174 Counter lastIcacheStall; 175 176 // number of cycles stalled for I-cache retries 177 Stats::Scalar<> icacheRetryCycles; 178 Counter lastIcacheRetry; 179 180 // number of cycles stalled for D-cache responses 181 Stats::Scalar<> dcacheStallCycles; 182 Counter lastDcacheStall; 183 184 // number of cycles stalled for D-cache retries 185 Stats::Scalar<> dcacheRetryCycles; 186 Counter lastDcacheRetry; 187 188 virtual void serialize(std::ostream &os); 189 virtual void unserialize(Checkpoint *cp, const std::string §ion); 190 191 // These functions are only used in CPU models that split 192 // effective address computation from the actual memory access. 193 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 194 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); } 195 196 void prefetch(Addr addr, unsigned flags) 197 { 198 // need to do this... 199 } 200 201 void writeHint(Addr addr, int size, unsigned flags) 202 { 203 // need to do this... 204 } 205 206 Fault copySrcTranslate(Addr src); 207 208 Fault copy(Addr dest); 209 210 // The register accessor methods provide the index of the 211 // instruction's operand (e.g., 0 or 1), not the architectural 212 // register index, to simplify the implementation of register 213 // renaming. We find the architectural register index by indexing 214 // into the instruction's own operand index table. Note that a 215 // raw pointer to the StaticInst is provided instead of a 216 // ref-counted StaticInstPtr to redice overhead. This is fine as 217 // long as these methods don't copy the pointer into any long-term 218 // storage (which is pretty hard to imagine they would have reason 219 // to do). 220 221 uint64_t readIntReg(const StaticInst *si, int idx) 222 { 223 return thread->readIntReg(si->srcRegIdx(idx)); 224 } 225 226 FloatReg readFloatReg(const StaticInst *si, int idx, int width) 227 { 228 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 229 return thread->readFloatReg(reg_idx, width); 230 } 231 232 FloatReg readFloatReg(const StaticInst *si, int idx) 233 { 234 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 235 return thread->readFloatReg(reg_idx); 236 } 237 238 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) 239 { 240 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 241 return thread->readFloatRegBits(reg_idx, width); 242 } 243 244 FloatRegBits readFloatRegBits(const StaticInst *si, int idx) 245 { 246 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 247 return thread->readFloatRegBits(reg_idx); 248 } 249 250 void setIntReg(const StaticInst *si, int idx, uint64_t val) 251 { 252 thread->setIntReg(si->destRegIdx(idx), val); 253 } 254 255 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 256 { 257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 258 thread->setFloatReg(reg_idx, val, width); 259 } 260 261 void setFloatReg(const StaticInst *si, int idx, FloatReg val) 262 { 263 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 264 thread->setFloatReg(reg_idx, val); 265 } 266 267 void setFloatRegBits(const StaticInst *si, int idx, 268 FloatRegBits val, int width) 269 { 270 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 271 thread->setFloatRegBits(reg_idx, val, width); 272 } 273 274 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) 275 { 276 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 277 thread->setFloatRegBits(reg_idx, val); 278 } 279 280 uint64_t readPC() { return thread->readPC(); } 281 uint64_t readNextPC() { return thread->readNextPC(); } 282 uint64_t readNextNPC() { return thread->readNextNPC(); } 283 284 void setPC(uint64_t val) { thread->setPC(val); } 285 void setNextPC(uint64_t val) { thread->setNextPC(val); } 286 void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 287 288 MiscReg readMiscReg(int misc_reg) 289 { 290 return thread->readMiscReg(misc_reg); 291 } 292 293 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 294 { 295 return thread->readMiscRegWithEffect(misc_reg, fault); 296 } 297 298 Fault setMiscReg(int misc_reg, const MiscReg &val) 299 { 300 return thread->setMiscReg(misc_reg, val); 301 } 302 303 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 304 { 305 return thread->setMiscRegWithEffect(misc_reg, val); 306 } 307 308#if FULL_SYSTEM 309 Fault hwrei() { return thread->hwrei(); } 310 int readIntrFlag() { return thread->readIntrFlag(); } 311 void setIntrFlag(int val) { thread->setIntrFlag(val); } 312 bool inPalMode() { return thread->inPalMode(); } 313 void ev5_trap(Fault fault) { fault->invoke(tc); } 314 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 315#else 316 void syscall(int64_t callnum) { thread->syscall(callnum); } 317#endif 318 319 bool misspeculating() { return thread->misspeculating(); } 320 ThreadContext *tcBase() { return tc; } 321}; 322 323#endif // __CPU_SIMPLE_BASE_HH__ | 130 StaticInstPtr curStaticInst; 131 132 void checkForInterrupts(); 133 Fault setupFetchRequest(Request *req); 134 void preExecute(); 135 void postExecute(); 136 void advancePC(Fault fault); 137 138 virtual void deallocateContext(int thread_num); 139 virtual void haltContext(int thread_num); 140 141 // statistics 142 virtual void regStats(); 143 virtual void resetStats(); 144 145 // number of simulated instructions 146 Counter numInst; 147 Counter startNumInst; 148 Stats::Scalar<> numInsts; 149 150 virtual Counter totalInstructions() const 151 { 152 return numInst - startNumInst; 153 } 154 155 // number of simulated memory references 156 Stats::Scalar<> numMemRefs; 157 158 // number of simulated loads 159 Counter numLoad; 160 Counter startNumLoad; 161 162 // number of idle cycles 163 Stats::Average<> notIdleFraction; 164 Stats::Formula idleFraction; 165 166 // number of cycles stalled for I-cache responses 167 Stats::Scalar<> icacheStallCycles; 168 Counter lastIcacheStall; 169 170 // number of cycles stalled for I-cache retries 171 Stats::Scalar<> icacheRetryCycles; 172 Counter lastIcacheRetry; 173 174 // number of cycles stalled for D-cache responses 175 Stats::Scalar<> dcacheStallCycles; 176 Counter lastDcacheStall; 177 178 // number of cycles stalled for D-cache retries 179 Stats::Scalar<> dcacheRetryCycles; 180 Counter lastDcacheRetry; 181 182 virtual void serialize(std::ostream &os); 183 virtual void unserialize(Checkpoint *cp, const std::string §ion); 184 185 // These functions are only used in CPU models that split 186 // effective address computation from the actual memory access. 187 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 188 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); } 189 190 void prefetch(Addr addr, unsigned flags) 191 { 192 // need to do this... 193 } 194 195 void writeHint(Addr addr, int size, unsigned flags) 196 { 197 // need to do this... 198 } 199 200 Fault copySrcTranslate(Addr src); 201 202 Fault copy(Addr dest); 203 204 // The register accessor methods provide the index of the 205 // instruction's operand (e.g., 0 or 1), not the architectural 206 // register index, to simplify the implementation of register 207 // renaming. We find the architectural register index by indexing 208 // into the instruction's own operand index table. Note that a 209 // raw pointer to the StaticInst is provided instead of a 210 // ref-counted StaticInstPtr to redice overhead. This is fine as 211 // long as these methods don't copy the pointer into any long-term 212 // storage (which is pretty hard to imagine they would have reason 213 // to do). 214 215 uint64_t readIntReg(const StaticInst *si, int idx) 216 { 217 return thread->readIntReg(si->srcRegIdx(idx)); 218 } 219 220 FloatReg readFloatReg(const StaticInst *si, int idx, int width) 221 { 222 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 223 return thread->readFloatReg(reg_idx, width); 224 } 225 226 FloatReg readFloatReg(const StaticInst *si, int idx) 227 { 228 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 229 return thread->readFloatReg(reg_idx); 230 } 231 232 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) 233 { 234 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 235 return thread->readFloatRegBits(reg_idx, width); 236 } 237 238 FloatRegBits readFloatRegBits(const StaticInst *si, int idx) 239 { 240 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 241 return thread->readFloatRegBits(reg_idx); 242 } 243 244 void setIntReg(const StaticInst *si, int idx, uint64_t val) 245 { 246 thread->setIntReg(si->destRegIdx(idx), val); 247 } 248 249 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 250 { 251 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 252 thread->setFloatReg(reg_idx, val, width); 253 } 254 255 void setFloatReg(const StaticInst *si, int idx, FloatReg val) 256 { 257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 258 thread->setFloatReg(reg_idx, val); 259 } 260 261 void setFloatRegBits(const StaticInst *si, int idx, 262 FloatRegBits val, int width) 263 { 264 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 265 thread->setFloatRegBits(reg_idx, val, width); 266 } 267 268 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) 269 { 270 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 271 thread->setFloatRegBits(reg_idx, val); 272 } 273 274 uint64_t readPC() { return thread->readPC(); } 275 uint64_t readNextPC() { return thread->readNextPC(); } 276 uint64_t readNextNPC() { return thread->readNextNPC(); } 277 278 void setPC(uint64_t val) { thread->setPC(val); } 279 void setNextPC(uint64_t val) { thread->setNextPC(val); } 280 void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 281 282 MiscReg readMiscReg(int misc_reg) 283 { 284 return thread->readMiscReg(misc_reg); 285 } 286 287 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 288 { 289 return thread->readMiscRegWithEffect(misc_reg, fault); 290 } 291 292 Fault setMiscReg(int misc_reg, const MiscReg &val) 293 { 294 return thread->setMiscReg(misc_reg, val); 295 } 296 297 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 298 { 299 return thread->setMiscRegWithEffect(misc_reg, val); 300 } 301 302#if FULL_SYSTEM 303 Fault hwrei() { return thread->hwrei(); } 304 int readIntrFlag() { return thread->readIntrFlag(); } 305 void setIntrFlag(int val) { thread->setIntrFlag(val); } 306 bool inPalMode() { return thread->inPalMode(); } 307 void ev5_trap(Fault fault) { fault->invoke(tc); } 308 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 309#else 310 void syscall(int64_t callnum) { thread->syscall(callnum); } 311#endif 312 313 bool misspeculating() { return thread->misspeculating(); } 314 ThreadContext *tcBase() { return tc; } 315}; 316 317#endif // __CPU_SIMPLE_BASE_HH__ |