1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
27 */
28
29#ifndef __CPU_SIMPLE_BASE_HH__
30#define __CPU_SIMPLE_BASE_HH__
31
32#include "base/statistics.hh"
33#include "config/full_system.hh"
34#include "cpu/base.hh"
35#include "cpu/cpu_exec_context.hh"
36#include "cpu/pc_event.hh"
37#include "cpu/sampler/sampler.hh"
38#include "cpu/static_inst.hh"
39#include "mem/packet.hh"
40#include "mem/port.hh"
41#include "mem/request.hh"
42#include "sim/eventq.hh"
43
44// forward declarations
45#if FULL_SYSTEM
46class Processor;
47class AlphaITB;
48class AlphaDTB;
49class MemObject;
50
51class RemoteGDB;
52class GDBListener;
53
54#else
55
56class Process;
57
58#endif // FULL_SYSTEM
59
60class ExecContext;
61class Checkpoint;
62
63namespace Trace {
64 class InstRecord;
65}
66
67
68class BaseSimpleCPU : public BaseCPU
69{
70 protected:
71 typedef TheISA::MachInst MachInst;
72 typedef TheISA::MiscReg MiscReg;
73 typedef TheISA::FloatReg FloatReg;
74 typedef TheISA::FloatRegBits FloatRegBits;
75
76 MemObject *mem;
77
78 protected:
79 Trace::InstRecord *traceData;
80
81 public:
82 void post_interrupt(int int_num, int index);
83
84 void zero_fill_64(Addr addr) {
85 static int warned = 0;
86 if (!warned) {
87 warn ("WH64 is not implemented");
88 warned = 1;
89 }
90 };
91
92 public:
93 struct Params : public BaseCPU::Params
94 {
95 MemObject *mem;
96#if FULL_SYSTEM
97 AlphaITB *itb;
98 AlphaDTB *dtb;
99#else
100 Process *process;
101#endif
102 };
103 BaseSimpleCPU(Params *params);
104 virtual ~BaseSimpleCPU();
105
106 public:
107 // execution context
108 CPUExecContext *cpuXC;
109
110 ExecContext *xcProxy;
111
112#if FULL_SYSTEM
113 Addr dbg_vtophys(Addr addr);
114
115 bool interval_stats;
116#endif
117
118 // current instruction
119 MachInst inst;
120
121 // Static data storage
122 TheISA::IntReg dataReg;
123
124 // Pointer to the sampler that is telling us to switchover.
125 // Used to signal the completion of the pipe drain and schedule
126 // the next switchover
127 Sampler *sampler;
128
129 StaticInstPtr curStaticInst;
130
131 void checkForInterrupts();
132 Fault setupFetchRequest(Request *req);
133 void preExecute();
134 void postExecute();
135 void advancePC(Fault fault);
136
137 virtual void deallocateContext(int thread_num);
138 virtual void haltContext(int thread_num);
139
140 // statistics
141 virtual void regStats();
142 virtual void resetStats();
143
144 // number of simulated instructions
145 Counter numInst;
146 Counter startNumInst;
147 Stats::Scalar<> numInsts;
148
149 virtual Counter totalInstructions() const
150 {
151 return numInst - startNumInst;
152 }
153
154 // number of simulated memory references
155 Stats::Scalar<> numMemRefs;
156
157 // number of simulated loads
158 Counter numLoad;
159 Counter startNumLoad;
160
161 // number of idle cycles
162 Stats::Average<> notIdleFraction;
163 Stats::Formula idleFraction;
164
165 // number of cycles stalled for I-cache responses
166 Stats::Scalar<> icacheStallCycles;
167 Counter lastIcacheStall;
168
169 // number of cycles stalled for I-cache retries
170 Stats::Scalar<> icacheRetryCycles;
171 Counter lastIcacheRetry;
172
173 // number of cycles stalled for D-cache responses
174 Stats::Scalar<> dcacheStallCycles;
175 Counter lastDcacheStall;
176
177 // number of cycles stalled for D-cache retries
178 Stats::Scalar<> dcacheRetryCycles;
179 Counter lastDcacheRetry;
180
181 virtual void serialize(std::ostream &os);
182 virtual void unserialize(Checkpoint *cp, const std::string §ion);
183
184 // These functions are only used in CPU models that split
185 // effective address computation from the actual memory access.
186 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
187 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); }
188
189 void prefetch(Addr addr, unsigned flags)
190 {
191 // need to do this...
192 }
193
194 void writeHint(Addr addr, int size, unsigned flags)
195 {
196 // need to do this...
197 }
198
199 Fault copySrcTranslate(Addr src);
200
201 Fault copy(Addr dest);
202
203 // The register accessor methods provide the index of the
204 // instruction's operand (e.g., 0 or 1), not the architectural
205 // register index, to simplify the implementation of register
206 // renaming. We find the architectural register index by indexing
207 // into the instruction's own operand index table. Note that a
208 // raw pointer to the StaticInst is provided instead of a
209 // ref-counted StaticInstPtr to redice overhead. This is fine as
210 // long as these methods don't copy the pointer into any long-term
211 // storage (which is pretty hard to imagine they would have reason
212 // to do).
213
214 uint64_t readIntReg(const StaticInst *si, int idx)
215 {
216 return cpuXC->readIntReg(si->srcRegIdx(idx));
217 }
218
219 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
220 {
221 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
222 return cpuXC->readFloatReg(reg_idx, width);
223 }
224
225 FloatReg readFloatReg(const StaticInst *si, int idx)
226 {
227 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
228 return cpuXC->readFloatReg(reg_idx);
229 }
230
231 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
232 {
233 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
234 return cpuXC->readFloatRegBits(reg_idx, width);
235 }
236
237 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
238 {
239 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
240 return cpuXC->readFloatRegBits(reg_idx);
241 }
242
243 void setIntReg(const StaticInst *si, int idx, uint64_t val)
244 {
245 cpuXC->setIntReg(si->destRegIdx(idx), val);
246 }
247
248 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
249 {
250 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
251 cpuXC->setFloatReg(reg_idx, val, width);
252 }
253
254 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
255 {
256 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
257 cpuXC->setFloatReg(reg_idx, val);
258 }
259
260 void setFloatRegBits(const StaticInst *si, int idx,
261 FloatRegBits val, int width)
262 {
263 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
264 cpuXC->setFloatRegBits(reg_idx, val, width);
265 }
266
267 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
268 {
269 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
270 cpuXC->setFloatRegBits(reg_idx, val);
271 }
272
273 uint64_t readPC() { return cpuXC->readPC(); }
274 uint64_t readNextPC() { return cpuXC->readNextPC(); }
275 uint64_t readNextNPC() { return cpuXC->readNextNPC(); }
276
277 void setPC(uint64_t val) { cpuXC->setPC(val); }
278 void setNextPC(uint64_t val) { cpuXC->setNextPC(val); }
279 void setNextNPC(uint64_t val) { cpuXC->setNextNPC(val); }
280
281 MiscReg readMiscReg(int misc_reg)
282 {
283 return cpuXC->readMiscReg(misc_reg);
284 }
285
286 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
287 {
288 return cpuXC->readMiscRegWithEffect(misc_reg, fault);
289 }
290
291 Fault setMiscReg(int misc_reg, const MiscReg &val)
292 {
293 return cpuXC->setMiscReg(misc_reg, val);
294 }
295
296 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
297 {
298 return cpuXC->setMiscRegWithEffect(misc_reg, val);
299 }
300
301#if FULL_SYSTEM
302 Fault hwrei() { return cpuXC->hwrei(); }
303 int readIntrFlag() { return cpuXC->readIntrFlag(); }
304 void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
305 bool inPalMode() { return cpuXC->inPalMode(); }
306 void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
307 bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
308#else
309 void syscall(int64_t callnum) { cpuXC->syscall(callnum); }
310#endif
311
312 bool misspeculating() { return cpuXC->misspeculating(); }
313 ExecContext *xcBase() { return xcProxy; }
314};
315
316#endif // __CPU_SIMPLE_BASE_HH__
| 31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "base/statistics.hh"
37#include "config/full_system.hh"
38#include "cpu/base.hh"
39#include "cpu/cpu_exec_context.hh"
40#include "cpu/pc_event.hh"
41#include "cpu/sampler/sampler.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51class AlphaITB;
52class AlphaDTB;
53class MemObject;
54
55class RemoteGDB;
56class GDBListener;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63
64class ExecContext;
65class Checkpoint;
66
67namespace Trace {
68 class InstRecord;
69}
70
71
72class BaseSimpleCPU : public BaseCPU
73{
74 protected:
75 typedef TheISA::MachInst MachInst;
76 typedef TheISA::MiscReg MiscReg;
77 typedef TheISA::FloatReg FloatReg;
78 typedef TheISA::FloatRegBits FloatRegBits;
79
80 MemObject *mem;
81
82 protected:
83 Trace::InstRecord *traceData;
84
85 public:
86 void post_interrupt(int int_num, int index);
87
88 void zero_fill_64(Addr addr) {
89 static int warned = 0;
90 if (!warned) {
91 warn ("WH64 is not implemented");
92 warned = 1;
93 }
94 };
95
96 public:
97 struct Params : public BaseCPU::Params
98 {
99 MemObject *mem;
100#if FULL_SYSTEM
101 AlphaITB *itb;
102 AlphaDTB *dtb;
103#else
104 Process *process;
105#endif
106 };
107 BaseSimpleCPU(Params *params);
108 virtual ~BaseSimpleCPU();
109
110 public:
111 // execution context
112 CPUExecContext *cpuXC;
113
114 ExecContext *xcProxy;
115
116#if FULL_SYSTEM
117 Addr dbg_vtophys(Addr addr);
118
119 bool interval_stats;
120#endif
121
122 // current instruction
123 MachInst inst;
124
125 // Static data storage
126 TheISA::IntReg dataReg;
127
128 // Pointer to the sampler that is telling us to switchover.
129 // Used to signal the completion of the pipe drain and schedule
130 // the next switchover
131 Sampler *sampler;
132
133 StaticInstPtr curStaticInst;
134
135 void checkForInterrupts();
136 Fault setupFetchRequest(Request *req);
137 void preExecute();
138 void postExecute();
139 void advancePC(Fault fault);
140
141 virtual void deallocateContext(int thread_num);
142 virtual void haltContext(int thread_num);
143
144 // statistics
145 virtual void regStats();
146 virtual void resetStats();
147
148 // number of simulated instructions
149 Counter numInst;
150 Counter startNumInst;
151 Stats::Scalar<> numInsts;
152
153 virtual Counter totalInstructions() const
154 {
155 return numInst - startNumInst;
156 }
157
158 // number of simulated memory references
159 Stats::Scalar<> numMemRefs;
160
161 // number of simulated loads
162 Counter numLoad;
163 Counter startNumLoad;
164
165 // number of idle cycles
166 Stats::Average<> notIdleFraction;
167 Stats::Formula idleFraction;
168
169 // number of cycles stalled for I-cache responses
170 Stats::Scalar<> icacheStallCycles;
171 Counter lastIcacheStall;
172
173 // number of cycles stalled for I-cache retries
174 Stats::Scalar<> icacheRetryCycles;
175 Counter lastIcacheRetry;
176
177 // number of cycles stalled for D-cache responses
178 Stats::Scalar<> dcacheStallCycles;
179 Counter lastDcacheStall;
180
181 // number of cycles stalled for D-cache retries
182 Stats::Scalar<> dcacheRetryCycles;
183 Counter lastDcacheRetry;
184
185 virtual void serialize(std::ostream &os);
186 virtual void unserialize(Checkpoint *cp, const std::string §ion);
187
188 // These functions are only used in CPU models that split
189 // effective address computation from the actual memory access.
190 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
191 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); }
192
193 void prefetch(Addr addr, unsigned flags)
194 {
195 // need to do this...
196 }
197
198 void writeHint(Addr addr, int size, unsigned flags)
199 {
200 // need to do this...
201 }
202
203 Fault copySrcTranslate(Addr src);
204
205 Fault copy(Addr dest);
206
207 // The register accessor methods provide the index of the
208 // instruction's operand (e.g., 0 or 1), not the architectural
209 // register index, to simplify the implementation of register
210 // renaming. We find the architectural register index by indexing
211 // into the instruction's own operand index table. Note that a
212 // raw pointer to the StaticInst is provided instead of a
213 // ref-counted StaticInstPtr to redice overhead. This is fine as
214 // long as these methods don't copy the pointer into any long-term
215 // storage (which is pretty hard to imagine they would have reason
216 // to do).
217
218 uint64_t readIntReg(const StaticInst *si, int idx)
219 {
220 return cpuXC->readIntReg(si->srcRegIdx(idx));
221 }
222
223 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
224 {
225 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
226 return cpuXC->readFloatReg(reg_idx, width);
227 }
228
229 FloatReg readFloatReg(const StaticInst *si, int idx)
230 {
231 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
232 return cpuXC->readFloatReg(reg_idx);
233 }
234
235 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
236 {
237 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
238 return cpuXC->readFloatRegBits(reg_idx, width);
239 }
240
241 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
242 {
243 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
244 return cpuXC->readFloatRegBits(reg_idx);
245 }
246
247 void setIntReg(const StaticInst *si, int idx, uint64_t val)
248 {
249 cpuXC->setIntReg(si->destRegIdx(idx), val);
250 }
251
252 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
253 {
254 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
255 cpuXC->setFloatReg(reg_idx, val, width);
256 }
257
258 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
259 {
260 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
261 cpuXC->setFloatReg(reg_idx, val);
262 }
263
264 void setFloatRegBits(const StaticInst *si, int idx,
265 FloatRegBits val, int width)
266 {
267 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
268 cpuXC->setFloatRegBits(reg_idx, val, width);
269 }
270
271 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
272 {
273 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
274 cpuXC->setFloatRegBits(reg_idx, val);
275 }
276
277 uint64_t readPC() { return cpuXC->readPC(); }
278 uint64_t readNextPC() { return cpuXC->readNextPC(); }
279 uint64_t readNextNPC() { return cpuXC->readNextNPC(); }
280
281 void setPC(uint64_t val) { cpuXC->setPC(val); }
282 void setNextPC(uint64_t val) { cpuXC->setNextPC(val); }
283 void setNextNPC(uint64_t val) { cpuXC->setNextNPC(val); }
284
285 MiscReg readMiscReg(int misc_reg)
286 {
287 return cpuXC->readMiscReg(misc_reg);
288 }
289
290 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
291 {
292 return cpuXC->readMiscRegWithEffect(misc_reg, fault);
293 }
294
295 Fault setMiscReg(int misc_reg, const MiscReg &val)
296 {
297 return cpuXC->setMiscReg(misc_reg, val);
298 }
299
300 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
301 {
302 return cpuXC->setMiscRegWithEffect(misc_reg, val);
303 }
304
305#if FULL_SYSTEM
306 Fault hwrei() { return cpuXC->hwrei(); }
307 int readIntrFlag() { return cpuXC->readIntrFlag(); }
308 void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
309 bool inPalMode() { return cpuXC->inPalMode(); }
310 void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
311 bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
312#else
313 void syscall(int64_t callnum) { cpuXC->syscall(callnum); }
314#endif
315
316 bool misspeculating() { return cpuXC->misspeculating(); }
317 ExecContext *xcBase() { return xcProxy; }
318};
319
320#endif // __CPU_SIMPLE_BASE_HH__
|