base.hh (10193:d717abc806aa) base.hh (10319:4207f9bfcceb)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Dave Greene
43 * Nathan Binkert
44 */
45
46#ifndef __CPU_SIMPLE_BASE_HH__
47#define __CPU_SIMPLE_BASE_HH__
48
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/checker/cpu.hh"
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Dave Greene
43 * Nathan Binkert
44 */
45
46#ifndef __CPU_SIMPLE_BASE_HH__
47#define __CPU_SIMPLE_BASE_HH__
48
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/exec_context.hh"
53#include "cpu/pc_event.hh"
54#include "cpu/simple_thread.hh"
55#include "cpu/static_inst.hh"
56#include "mem/packet.hh"
57#include "mem/port.hh"
58#include "mem/request.hh"
59#include "sim/eventq.hh"
60#include "sim/full_system.hh"
61#include "sim/system.hh"
62
63// forward declarations
64class Checkpoint;
65class Process;
66class Processor;
67class ThreadContext;
68
69namespace TheISA
70{
71 class DTB;
72 class ITB;
73}
74
75namespace Trace {
76 class InstRecord;
77}
78
79struct BaseSimpleCPUParams;
80class BPredUnit;
81
54#include "cpu/pc_event.hh"
55#include "cpu/simple_thread.hh"
56#include "cpu/static_inst.hh"
57#include "mem/packet.hh"
58#include "mem/port.hh"
59#include "mem/request.hh"
60#include "sim/eventq.hh"
61#include "sim/full_system.hh"
62#include "sim/system.hh"
63
64// forward declarations
65class Checkpoint;
66class Process;
67class Processor;
68class ThreadContext;
69
70namespace TheISA
71{
72 class DTB;
73 class ITB;
74}
75
76namespace Trace {
77 class InstRecord;
78}
79
80struct BaseSimpleCPUParams;
81class BPredUnit;
82
82class BaseSimpleCPU : public BaseCPU
83class BaseSimpleCPU : public BaseCPU, public ExecContext
83{
84 protected:
85 typedef TheISA::MiscReg MiscReg;
86 typedef TheISA::FloatReg FloatReg;
87 typedef TheISA::FloatRegBits FloatRegBits;
88 typedef TheISA::CCReg CCReg;
89
90 BPredUnit *branchPred;
91
92 protected:
93 Trace::InstRecord *traceData;
94
95 inline void checkPcEventQueue() {
96 Addr oldpc, pc = thread->instAddr();
97 do {
98 oldpc = pc;
99 system->pcEventQueue.service(tc);
100 pc = thread->instAddr();
101 } while (oldpc != pc);
102 }
103
104 public:
105 void wakeup();
106
107 void zero_fill_64(Addr addr) {
108 static int warned = 0;
109 if (!warned) {
110 warn ("WH64 is not implemented");
111 warned = 1;
112 }
113 };
114
115 public:
116 BaseSimpleCPU(BaseSimpleCPUParams *params);
117 virtual ~BaseSimpleCPU();
118
119 public:
120 /** SimpleThread object, provides all the architectural state. */
121 SimpleThread *thread;
122
123 /** ThreadContext object, provides an interface for external
124 * objects to modify this thread's state.
125 */
126 ThreadContext *tc;
127
128 CheckerCPU *checker;
129
130 protected:
131
132 enum Status {
133 Idle,
134 Running,
135 Faulting,
136 ITBWaitResponse,
137 IcacheRetry,
138 IcacheWaitResponse,
139 IcacheWaitSwitch,
140 DTBWaitResponse,
141 DcacheRetry,
142 DcacheWaitResponse,
143 DcacheWaitSwitch,
144 };
145
146 Status _status;
147
148 public:
149
150 Addr dbg_vtophys(Addr addr);
151
152 bool interval_stats;
153
154 // current instruction
155 TheISA::MachInst inst;
156
157 StaticInstPtr curStaticInst;
158 StaticInstPtr curMacroStaticInst;
159
160 //This is the offset from the current pc that fetch should be performed at
161 Addr fetchOffset;
162 //This flag says to stay at the current pc. This is useful for
163 //instructions which go beyond MachInst boundaries.
164 bool stayAtPC;
165
166 void checkForInterrupts();
167 void setupFetchRequest(Request *req);
168 void preExecute();
169 void postExecute();
170 void advancePC(Fault fault);
171
172 virtual void deallocateContext(ThreadID thread_num);
173 virtual void haltContext(ThreadID thread_num);
174
175 // statistics
176 virtual void regStats();
177 virtual void resetStats();
178
179 virtual void startup();
180
181 // number of simulated instructions
182 Counter numInst;
183 Counter startNumInst;
184 Stats::Scalar numInsts;
185 Counter numOp;
186 Counter startNumOp;
187 Stats::Scalar numOps;
188
189 void countInst()
190 {
191 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
192 numInst++;
193 numInsts++;
194 }
195 numOp++;
196 numOps++;
197
198 system->totalNumInsts++;
199 thread->funcExeInst++;
200 }
201
202 virtual Counter totalInsts() const
203 {
204 return numInst - startNumInst;
205 }
206
207 virtual Counter totalOps() const
208 {
209 return numOp - startNumOp;
210 }
211
212 //number of integer alu accesses
213 Stats::Scalar numIntAluAccesses;
214
215 //number of float alu accesses
216 Stats::Scalar numFpAluAccesses;
217
218 //number of function calls/returns
219 Stats::Scalar numCallsReturns;
220
221 //conditional control instructions;
222 Stats::Scalar numCondCtrlInsts;
223
224 //number of int instructions
225 Stats::Scalar numIntInsts;
226
227 //number of float instructions
228 Stats::Scalar numFpInsts;
229
230 //number of integer register file accesses
231 Stats::Scalar numIntRegReads;
232 Stats::Scalar numIntRegWrites;
233
234 //number of float register file accesses
235 Stats::Scalar numFpRegReads;
236 Stats::Scalar numFpRegWrites;
237
238 //number of condition code register file accesses
239 Stats::Scalar numCCRegReads;
240 Stats::Scalar numCCRegWrites;
241
242 // number of simulated memory references
243 Stats::Scalar numMemRefs;
244 Stats::Scalar numLoadInsts;
245 Stats::Scalar numStoreInsts;
246
247 // number of idle cycles
248 Stats::Formula numIdleCycles;
249
250 // number of busy cycles
251 Stats::Formula numBusyCycles;
252
253 // number of simulated loads
254 Counter numLoad;
255 Counter startNumLoad;
256
257 // number of idle cycles
258 Stats::Average notIdleFraction;
259 Stats::Formula idleFraction;
260
261 // number of cycles stalled for I-cache responses
262 Stats::Scalar icacheStallCycles;
263 Counter lastIcacheStall;
264
265 // number of cycles stalled for I-cache retries
266 Stats::Scalar icacheRetryCycles;
267 Counter lastIcacheRetry;
268
269 // number of cycles stalled for D-cache responses
270 Stats::Scalar dcacheStallCycles;
271 Counter lastDcacheStall;
272
273 // number of cycles stalled for D-cache retries
274 Stats::Scalar dcacheRetryCycles;
275 Counter lastDcacheRetry;
276
277 /// @{
278 /// Total number of branches fetched
279 Stats::Scalar numBranches;
280 /// Number of branches predicted as taken
281 Stats::Scalar numPredictedBranches;
282 /// Number of misprediced branches
283 Stats::Scalar numBranchMispred;
284 /// @}
285
286 // instruction mix histogram by OpClass
287 Stats::Vector statExecutedInstType;
288
289 void serializeThread(std::ostream &os, ThreadID tid);
290 void unserializeThread(Checkpoint *cp, const std::string &section,
291 ThreadID tid);
292
293 // These functions are only used in CPU models that split
294 // effective address computation from the actual memory access.
295 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
84{
85 protected:
86 typedef TheISA::MiscReg MiscReg;
87 typedef TheISA::FloatReg FloatReg;
88 typedef TheISA::FloatRegBits FloatRegBits;
89 typedef TheISA::CCReg CCReg;
90
91 BPredUnit *branchPred;
92
93 protected:
94 Trace::InstRecord *traceData;
95
96 inline void checkPcEventQueue() {
97 Addr oldpc, pc = thread->instAddr();
98 do {
99 oldpc = pc;
100 system->pcEventQueue.service(tc);
101 pc = thread->instAddr();
102 } while (oldpc != pc);
103 }
104
105 public:
106 void wakeup();
107
108 void zero_fill_64(Addr addr) {
109 static int warned = 0;
110 if (!warned) {
111 warn ("WH64 is not implemented");
112 warned = 1;
113 }
114 };
115
116 public:
117 BaseSimpleCPU(BaseSimpleCPUParams *params);
118 virtual ~BaseSimpleCPU();
119
120 public:
121 /** SimpleThread object, provides all the architectural state. */
122 SimpleThread *thread;
123
124 /** ThreadContext object, provides an interface for external
125 * objects to modify this thread's state.
126 */
127 ThreadContext *tc;
128
129 CheckerCPU *checker;
130
131 protected:
132
133 enum Status {
134 Idle,
135 Running,
136 Faulting,
137 ITBWaitResponse,
138 IcacheRetry,
139 IcacheWaitResponse,
140 IcacheWaitSwitch,
141 DTBWaitResponse,
142 DcacheRetry,
143 DcacheWaitResponse,
144 DcacheWaitSwitch,
145 };
146
147 Status _status;
148
149 public:
150
151 Addr dbg_vtophys(Addr addr);
152
153 bool interval_stats;
154
155 // current instruction
156 TheISA::MachInst inst;
157
158 StaticInstPtr curStaticInst;
159 StaticInstPtr curMacroStaticInst;
160
161 //This is the offset from the current pc that fetch should be performed at
162 Addr fetchOffset;
163 //This flag says to stay at the current pc. This is useful for
164 //instructions which go beyond MachInst boundaries.
165 bool stayAtPC;
166
167 void checkForInterrupts();
168 void setupFetchRequest(Request *req);
169 void preExecute();
170 void postExecute();
171 void advancePC(Fault fault);
172
173 virtual void deallocateContext(ThreadID thread_num);
174 virtual void haltContext(ThreadID thread_num);
175
176 // statistics
177 virtual void regStats();
178 virtual void resetStats();
179
180 virtual void startup();
181
182 // number of simulated instructions
183 Counter numInst;
184 Counter startNumInst;
185 Stats::Scalar numInsts;
186 Counter numOp;
187 Counter startNumOp;
188 Stats::Scalar numOps;
189
190 void countInst()
191 {
192 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
193 numInst++;
194 numInsts++;
195 }
196 numOp++;
197 numOps++;
198
199 system->totalNumInsts++;
200 thread->funcExeInst++;
201 }
202
203 virtual Counter totalInsts() const
204 {
205 return numInst - startNumInst;
206 }
207
208 virtual Counter totalOps() const
209 {
210 return numOp - startNumOp;
211 }
212
213 //number of integer alu accesses
214 Stats::Scalar numIntAluAccesses;
215
216 //number of float alu accesses
217 Stats::Scalar numFpAluAccesses;
218
219 //number of function calls/returns
220 Stats::Scalar numCallsReturns;
221
222 //conditional control instructions;
223 Stats::Scalar numCondCtrlInsts;
224
225 //number of int instructions
226 Stats::Scalar numIntInsts;
227
228 //number of float instructions
229 Stats::Scalar numFpInsts;
230
231 //number of integer register file accesses
232 Stats::Scalar numIntRegReads;
233 Stats::Scalar numIntRegWrites;
234
235 //number of float register file accesses
236 Stats::Scalar numFpRegReads;
237 Stats::Scalar numFpRegWrites;
238
239 //number of condition code register file accesses
240 Stats::Scalar numCCRegReads;
241 Stats::Scalar numCCRegWrites;
242
243 // number of simulated memory references
244 Stats::Scalar numMemRefs;
245 Stats::Scalar numLoadInsts;
246 Stats::Scalar numStoreInsts;
247
248 // number of idle cycles
249 Stats::Formula numIdleCycles;
250
251 // number of busy cycles
252 Stats::Formula numBusyCycles;
253
254 // number of simulated loads
255 Counter numLoad;
256 Counter startNumLoad;
257
258 // number of idle cycles
259 Stats::Average notIdleFraction;
260 Stats::Formula idleFraction;
261
262 // number of cycles stalled for I-cache responses
263 Stats::Scalar icacheStallCycles;
264 Counter lastIcacheStall;
265
266 // number of cycles stalled for I-cache retries
267 Stats::Scalar icacheRetryCycles;
268 Counter lastIcacheRetry;
269
270 // number of cycles stalled for D-cache responses
271 Stats::Scalar dcacheStallCycles;
272 Counter lastDcacheStall;
273
274 // number of cycles stalled for D-cache retries
275 Stats::Scalar dcacheRetryCycles;
276 Counter lastDcacheRetry;
277
278 /// @{
279 /// Total number of branches fetched
280 Stats::Scalar numBranches;
281 /// Number of branches predicted as taken
282 Stats::Scalar numPredictedBranches;
283 /// Number of misprediced branches
284 Stats::Scalar numBranchMispred;
285 /// @}
286
287 // instruction mix histogram by OpClass
288 Stats::Vector statExecutedInstType;
289
290 void serializeThread(std::ostream &os, ThreadID tid);
291 void unserializeThread(Checkpoint *cp, const std::string &section,
292 ThreadID tid);
293
294 // These functions are only used in CPU models that split
295 // effective address computation from the actual memory access.
296 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
296 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
297 M5_DUMMY_RETURN}
297 Addr getEA() const { panic("BaseSimpleCPU::getEA() not implemented\n"); }
298
299 // The register accessor methods provide the index of the
300 // instruction's operand (e.g., 0 or 1), not the architectural
301 // register index, to simplify the implementation of register
302 // renaming. We find the architectural register index by indexing
303 // into the instruction's own operand index table. Note that a
304 // raw pointer to the StaticInst is provided instead of a
305 // ref-counted StaticInstPtr to redice overhead. This is fine as
306 // long as these methods don't copy the pointer into any long-term
307 // storage (which is pretty hard to imagine they would have reason
308 // to do).
309
298
299 // The register accessor methods provide the index of the
300 // instruction's operand (e.g., 0 or 1), not the architectural
301 // register index, to simplify the implementation of register
302 // renaming. We find the architectural register index by indexing
303 // into the instruction's own operand index table. Note that a
304 // raw pointer to the StaticInst is provided instead of a
305 // ref-counted StaticInstPtr to redice overhead. This is fine as
306 // long as these methods don't copy the pointer into any long-term
307 // storage (which is pretty hard to imagine they would have reason
308 // to do).
309
310 uint64_t readIntRegOperand(const StaticInst *si, int idx)
310 IntReg readIntRegOperand(const StaticInst *si, int idx)
311 {
312 numIntRegReads++;
313 return thread->readIntReg(si->srcRegIdx(idx));
314 }
315
316 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
317 {
318 numFpRegReads++;
319 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
320 return thread->readFloatReg(reg_idx);
321 }
322
323 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
324 {
325 numFpRegReads++;
326 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
327 return thread->readFloatRegBits(reg_idx);
328 }
329
330 CCReg readCCRegOperand(const StaticInst *si, int idx)
331 {
332 numCCRegReads++;
333 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
334 return thread->readCCReg(reg_idx);
335 }
336
311 {
312 numIntRegReads++;
313 return thread->readIntReg(si->srcRegIdx(idx));
314 }
315
316 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
317 {
318 numFpRegReads++;
319 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
320 return thread->readFloatReg(reg_idx);
321 }
322
323 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
324 {
325 numFpRegReads++;
326 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
327 return thread->readFloatRegBits(reg_idx);
328 }
329
330 CCReg readCCRegOperand(const StaticInst *si, int idx)
331 {
332 numCCRegReads++;
333 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
334 return thread->readCCReg(reg_idx);
335 }
336
337 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
337 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
338 {
339 numIntRegWrites++;
340 thread->setIntReg(si->destRegIdx(idx), val);
341 }
342
343 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
344 {
345 numFpRegWrites++;
346 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
347 thread->setFloatReg(reg_idx, val);
348 }
349
350 void setFloatRegOperandBits(const StaticInst *si, int idx,
351 FloatRegBits val)
352 {
353 numFpRegWrites++;
354 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
355 thread->setFloatRegBits(reg_idx, val);
356 }
357
358 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
359 {
360 numCCRegWrites++;
361 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
362 thread->setCCReg(reg_idx, val);
363 }
364
365 bool readPredicate() { return thread->readPredicate(); }
366 void setPredicate(bool val)
367 {
368 thread->setPredicate(val);
369 if (traceData) {
370 traceData->setPredicate(val);
371 }
372 }
338 {
339 numIntRegWrites++;
340 thread->setIntReg(si->destRegIdx(idx), val);
341 }
342
343 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
344 {
345 numFpRegWrites++;
346 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
347 thread->setFloatReg(reg_idx, val);
348 }
349
350 void setFloatRegOperandBits(const StaticInst *si, int idx,
351 FloatRegBits val)
352 {
353 numFpRegWrites++;
354 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
355 thread->setFloatRegBits(reg_idx, val);
356 }
357
358 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
359 {
360 numCCRegWrites++;
361 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
362 thread->setCCReg(reg_idx, val);
363 }
364
365 bool readPredicate() { return thread->readPredicate(); }
366 void setPredicate(bool val)
367 {
368 thread->setPredicate(val);
369 if (traceData) {
370 traceData->setPredicate(val);
371 }
372 }
373 TheISA::PCState pcState() { return thread->pcState(); }
373 TheISA::PCState pcState() const { return thread->pcState(); }
374 void pcState(const TheISA::PCState &val) { thread->pcState(val); }
375 Addr instAddr() { return thread->instAddr(); }
376 Addr nextInstAddr() { return thread->nextInstAddr(); }
377 MicroPC microPC() { return thread->microPC(); }
378
379 MiscReg readMiscRegNoEffect(int misc_reg)
380 {
381 return thread->readMiscRegNoEffect(misc_reg);
382 }
383
384 MiscReg readMiscReg(int misc_reg)
385 {
386 numIntRegReads++;
387 return thread->readMiscReg(misc_reg);
388 }
389
390 void setMiscReg(int misc_reg, const MiscReg &val)
391 {
392 numIntRegWrites++;
393 return thread->setMiscReg(misc_reg, val);
394 }
395
396 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
397 {
398 numIntRegReads++;
399 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
400 return thread->readMiscReg(reg_idx);
401 }
402
403 void setMiscRegOperand(
404 const StaticInst *si, int idx, const MiscReg &val)
405 {
406 numIntRegWrites++;
407 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
408 return thread->setMiscReg(reg_idx, val);
409 }
410
411 void demapPage(Addr vaddr, uint64_t asn)
412 {
413 thread->demapPage(vaddr, asn);
414 }
415
416 void demapInstPage(Addr vaddr, uint64_t asn)
417 {
418 thread->demapInstPage(vaddr, asn);
419 }
420
421 void demapDataPage(Addr vaddr, uint64_t asn)
422 {
423 thread->demapDataPage(vaddr, asn);
424 }
425
374 void pcState(const TheISA::PCState &val) { thread->pcState(val); }
375 Addr instAddr() { return thread->instAddr(); }
376 Addr nextInstAddr() { return thread->nextInstAddr(); }
377 MicroPC microPC() { return thread->microPC(); }
378
379 MiscReg readMiscRegNoEffect(int misc_reg)
380 {
381 return thread->readMiscRegNoEffect(misc_reg);
382 }
383
384 MiscReg readMiscReg(int misc_reg)
385 {
386 numIntRegReads++;
387 return thread->readMiscReg(misc_reg);
388 }
389
390 void setMiscReg(int misc_reg, const MiscReg &val)
391 {
392 numIntRegWrites++;
393 return thread->setMiscReg(misc_reg, val);
394 }
395
396 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
397 {
398 numIntRegReads++;
399 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
400 return thread->readMiscReg(reg_idx);
401 }
402
403 void setMiscRegOperand(
404 const StaticInst *si, int idx, const MiscReg &val)
405 {
406 numIntRegWrites++;
407 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
408 return thread->setMiscReg(reg_idx, val);
409 }
410
411 void demapPage(Addr vaddr, uint64_t asn)
412 {
413 thread->demapPage(vaddr, asn);
414 }
415
416 void demapInstPage(Addr vaddr, uint64_t asn)
417 {
418 thread->demapInstPage(vaddr, asn);
419 }
420
421 void demapDataPage(Addr vaddr, uint64_t asn)
422 {
423 thread->demapDataPage(vaddr, asn);
424 }
425
426 unsigned readStCondFailures() {
426 unsigned int readStCondFailures() const {
427 return thread->readStCondFailures();
428 }
429
427 return thread->readStCondFailures();
428 }
429
430 void setStCondFailures(unsigned sc_failures) {
430 void setStCondFailures(unsigned int sc_failures) {
431 thread->setStCondFailures(sc_failures);
432 }
433
431 thread->setStCondFailures(sc_failures);
432 }
433
434 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
435 {
434 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
435 {
436 panic("Simple CPU models do not support multithreaded "
437 "register access.\n");
436 panic("Simple CPU models do not support multithreaded "
437 "register access.\n");
438 }
438 }
439
439
440 void setRegOtherThread(int regIdx, const MiscReg &val,
441 ThreadID tid = InvalidThreadID)
442 {
440 void setRegOtherThread(int regIdx, MiscReg val,
441 ThreadID tid = InvalidThreadID)
442 {
443 panic("Simple CPU models do not support multithreaded "
444 "register access.\n");
443 panic("Simple CPU models do not support multithreaded "
444 "register access.\n");
445 }
445 }
446
447 //Fault CacheOp(uint8_t Op, Addr EA);
448
449 Fault hwrei() { return thread->hwrei(); }
450 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
451
452 void
453 syscall(int64_t callnum)
454 {
455 if (FullSystem)
456 panic("Syscall emulation isn't available in FS mode.\n");
457
458 thread->syscall(callnum);
459 }
460
461 bool misspeculating() { return thread->misspeculating(); }
462 ThreadContext *tcBase() { return tc; }
463
464 private:
465 TheISA::PCState pred_pc;
466};
467
468#endif // __CPU_SIMPLE_BASE_HH__
446
447 //Fault CacheOp(uint8_t Op, Addr EA);
448
449 Fault hwrei() { return thread->hwrei(); }
450 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
451
452 void
453 syscall(int64_t callnum)
454 {
455 if (FullSystem)
456 panic("Syscall emulation isn't available in FS mode.\n");
457
458 thread->syscall(callnum);
459 }
460
461 bool misspeculating() { return thread->misspeculating(); }
462 ThreadContext *tcBase() { return tc; }
463
464 private:
465 TheISA::PCState pred_pc;
466};
467
468#endif // __CPU_SIMPLE_BASE_HH__