1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 40 unchanged lines hidden (view full) ---

49class Processor;
50namespace TheISA
51{
52 class ITB;
53 class DTB;
54}
55class MemObject;
56
57class RemoteGDB;
58class GDBListener;
59
60#else
61
62class Process;
63
64#endif // FULL_SYSTEM
65
66class ThreadContext;
67class Checkpoint;
68
69namespace Trace {
70 class InstRecord;
71}
72
73

--- 107 unchanged lines hidden (view full) ---

181 Counter lastDcacheRetry;
182
183 virtual void serialize(std::ostream &os);
184 virtual void unserialize(Checkpoint *cp, const std::string &section);
185
186 // These functions are only used in CPU models that split
187 // effective address computation from the actual memory access.
188 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
189 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
190 M5_DUMMY_RETURN}
191
192 void prefetch(Addr addr, unsigned flags)
193 {
194 // need to do this...
195 }
196
197 void writeHint(Addr addr, int size, unsigned flags)
198 {

--- 100 unchanged lines hidden (view full) ---

299 return thread->setMiscReg(misc_reg, val);
300 }
301
302 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
303 {
304 return thread->setMiscRegWithEffect(misc_reg, val);
305 }
306
307#if FULL_SYSTEM
308 Fault hwrei() { return thread->hwrei(); }
309 void ev5_trap(Fault fault) { fault->invoke(tc); }
310 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
311#else
312 void syscall(int64_t callnum) { thread->syscall(callnum); }
313#endif
314
315 bool misspeculating() { return thread->misspeculating(); }
316 ThreadContext *tcBase() { return tc; }
317};
318
319#endif // __CPU_SIMPLE_BASE_HH__