1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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74class BaseSimpleCPU : public BaseCPU
75{
76 protected:
77 typedef TheISA::MachInst MachInst;
78 typedef TheISA::MiscReg MiscReg;
79 typedef TheISA::FloatReg FloatReg;
80 typedef TheISA::FloatRegBits FloatRegBits;
81
82 MemObject *mem;
83
84 protected:
85 Trace::InstRecord *traceData;
86
87 public:
88 void post_interrupt(int int_num, int index);
89
90 void zero_fill_64(Addr addr) {
91 static int warned = 0;
92 if (!warned) {
93 warn ("WH64 is not implemented");
94 warned = 1;
95 }
96 };
97
98 public:
99 struct Params : public BaseCPU::Params
100 {
101 MemObject *mem;
102#if FULL_SYSTEM
103 TheISA::ITB *itb;
104 TheISA::DTB *dtb;
105#else
106 Process *process;
107#endif
108 };
109 BaseSimpleCPU(Params *params);

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