1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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71class BaseSimpleCPU : public BaseCPU
72{
73 protected:
74 typedef TheISA::MachInst MachInst;
75 typedef TheISA::MiscReg MiscReg;
76 typedef TheISA::FloatReg FloatReg;
77 typedef TheISA::FloatRegBits FloatRegBits;
78
79 MemObject *mem;
80
81 protected:
82 Trace::InstRecord *traceData;
83
84 public:
85 void post_interrupt(int int_num, int index);
86
87 void zero_fill_64(Addr addr) {
88 static int warned = 0;
89 if (!warned) {
90 warn ("WH64 is not implemented");
91 warned = 1;
92 }
93 };
94
95 public:
96 struct Params : public BaseCPU::Params
97 {
98 MemObject *mem;
99#if FULL_SYSTEM
100 AlphaITB *itb;
101 AlphaDTB *dtb;
102#else
103 Process *process;
104#endif
105 };
106 BaseSimpleCPU(Params *params);

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