1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47#include "sim/system.hh"
48
49// forward declarations
50#if FULL_SYSTEM
51class Processor;
52namespace TheISA
53{
54 class ITB;
55 class DTB;
56}
57class MemObject;
58
59#else
60
61class Process;
62
63#endif // FULL_SYSTEM
64
65class RemoteGDB;
66class GDBListener;
67
68namespace TheISA
69{
70 class Predecoder;
71}
72class ThreadContext;
73class Checkpoint;
74
75namespace Trace {
76 class InstRecord;
77}
78
79
80class BaseSimpleCPU : public BaseCPU
81{
82 protected:
83 typedef TheISA::MiscReg MiscReg;
84 typedef TheISA::FloatReg FloatReg;
85 typedef TheISA::FloatRegBits FloatRegBits;
86
87 protected:
88 Trace::InstRecord *traceData;
89
90 inline void checkPcEventQueue() {
91 Addr oldpc;
92 do {
93 oldpc = thread->readPC();
94 system->pcEventQueue.service(tc);
95 } while (oldpc != thread->readPC());
96 }
97
98 public:
99 void post_interrupt(int int_num, int index);
100
101 void zero_fill_64(Addr addr) {
102 static int warned = 0;
103 if (!warned) {
104 warn ("WH64 is not implemented");
105 warned = 1;
106 }
107 };
108
109 public:
110 struct Params : public BaseCPU::Params
111 {
112 TheISA::ITB *itb;
113 TheISA::DTB *dtb;
114#if !FULL_SYSTEM
115 Process *process;
116#endif
117 };
118 BaseSimpleCPU(Params *params);
119 virtual ~BaseSimpleCPU();
120
121 public:
122 /** SimpleThread object, provides all the architectural state. */
123 SimpleThread *thread;
124
125 /** ThreadContext object, provides an interface for external
126 * objects to modify this thread's state.
127 */
128 ThreadContext *tc;
129 protected:
130 int cpuId;
131
132 public:
133
134#if FULL_SYSTEM
135 Addr dbg_vtophys(Addr addr);
136
137 bool interval_stats;
138#endif
139
140 // current instruction
141 TheISA::MachInst inst;
142
143 // The predecoder
144 TheISA::Predecoder predecoder;
145
146 StaticInstPtr curStaticInst;
147 StaticInstPtr curMacroStaticInst;
148
149 //This is the offset from the current pc that fetch should be performed at
150 Addr fetchOffset;
151 //This flag says to stay at the current pc. This is useful for
152 //instructions which go beyond MachInst boundaries.
153 bool stayAtPC;
154
155 void checkForInterrupts();
156 Fault setupFetchRequest(Request *req);
157 void preExecute();
158 void postExecute();
159 void advancePC(Fault fault);
160
161 virtual void deallocateContext(int thread_num);
162 virtual void haltContext(int thread_num);
163
164 // statistics
165 virtual void regStats();
166 virtual void resetStats();
167
168 // number of simulated instructions
169 Counter numInst;
170 Counter startNumInst;
171 Stats::Scalar<> numInsts;
172
173 void countInst()
174 {
175 numInst++;
176 numInsts++;
177
178 thread->funcExeInst++;
179 }
180
181 virtual Counter totalInstructions() const
182 {
183 return numInst - startNumInst;
184 }
185
186 // Mask to align PCs to MachInst sized boundaries
187 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
188
189 // number of simulated memory references
190 Stats::Scalar<> numMemRefs;
191
192 // number of simulated loads
193 Counter numLoad;
194 Counter startNumLoad;
195
196 // number of idle cycles
197 Stats::Average<> notIdleFraction;
198 Stats::Formula idleFraction;
199
200 // number of cycles stalled for I-cache responses
201 Stats::Scalar<> icacheStallCycles;
202 Counter lastIcacheStall;
203
204 // number of cycles stalled for I-cache retries
205 Stats::Scalar<> icacheRetryCycles;
206 Counter lastIcacheRetry;
207
208 // number of cycles stalled for D-cache responses
209 Stats::Scalar<> dcacheStallCycles;
210 Counter lastDcacheStall;
211
212 // number of cycles stalled for D-cache retries
213 Stats::Scalar<> dcacheRetryCycles;
214 Counter lastDcacheRetry;
215
216 virtual void serialize(std::ostream &os);
217 virtual void unserialize(Checkpoint *cp, const std::string &section);
218
219 // These functions are only used in CPU models that split
220 // effective address computation from the actual memory access.
221 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
222 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
223 M5_DUMMY_RETURN}
224
225 void prefetch(Addr addr, unsigned flags)
226 {
227 // need to do this...
228 }
229
230 void writeHint(Addr addr, int size, unsigned flags)
231 {
232 // need to do this...
233 }
234
235
236 Fault copySrcTranslate(Addr src);
237
238 Fault copy(Addr dest);
239
240 // The register accessor methods provide the index of the
241 // instruction's operand (e.g., 0 or 1), not the architectural
242 // register index, to simplify the implementation of register
243 // renaming. We find the architectural register index by indexing
244 // into the instruction's own operand index table. Note that a
245 // raw pointer to the StaticInst is provided instead of a
246 // ref-counted StaticInstPtr to redice overhead. This is fine as
247 // long as these methods don't copy the pointer into any long-term
248 // storage (which is pretty hard to imagine they would have reason
249 // to do).
250
251 uint64_t readIntRegOperand(const StaticInst *si, int idx)
252 {
253 return thread->readIntReg(si->srcRegIdx(idx));
254 }
255
256 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
257 {
258 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
259 return thread->readFloatReg(reg_idx, width);
260 }
261
262 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
263 {
264 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
265 return thread->readFloatReg(reg_idx);
266 }
267
268 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
269 int width)
270 {
271 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
272 return thread->readFloatRegBits(reg_idx, width);
273 }
274
275 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
276 {
277 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
278 return thread->readFloatRegBits(reg_idx);
279 }
280
281 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
282 {
283 thread->setIntReg(si->destRegIdx(idx), val);
284 }
285
286 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
287 int width)
288 {
289 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
290 thread->setFloatReg(reg_idx, val, width);
291 }
292
293 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
294 {
295 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
296 thread->setFloatReg(reg_idx, val);
297 }
298
299 void setFloatRegOperandBits(const StaticInst *si, int idx,
300 FloatRegBits val, int width)
301 {
302 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
303 thread->setFloatRegBits(reg_idx, val, width);
304 }
305
306 void setFloatRegOperandBits(const StaticInst *si, int idx,
307 FloatRegBits val)
308 {
309 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
310 thread->setFloatRegBits(reg_idx, val);
311 }
312
313 uint64_t readPC() { return thread->readPC(); }
314 uint64_t readMicroPC() { return thread->readMicroPC(); }
315 uint64_t readNextPC() { return thread->readNextPC(); }
316 uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
317 uint64_t readNextNPC() { return thread->readNextNPC(); }
318
319 void setPC(uint64_t val) { thread->setPC(val); }
320 void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
321 void setNextPC(uint64_t val) { thread->setNextPC(val); }
322 void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
323 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
324
325 MiscReg readMiscRegNoEffect(int misc_reg)
326 {
327 return thread->readMiscRegNoEffect(misc_reg);
328 }
329
330 MiscReg readMiscReg(int misc_reg)
331 {
332 return thread->readMiscReg(misc_reg);
333 }
334
335 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
336 {
337 return thread->setMiscRegNoEffect(misc_reg, val);
338 }
339
340 void setMiscReg(int misc_reg, const MiscReg &val)
341 {
342 return thread->setMiscReg(misc_reg, val);
343 }
344
345 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
346 {
347 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
348 return thread->readMiscRegNoEffect(reg_idx);
349 }
350
351 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
352 {
353 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
354 return thread->readMiscReg(reg_idx);
355 }
356
357 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
358 {
359 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
360 return thread->setMiscRegNoEffect(reg_idx, val);
361 }
362
363 void setMiscRegOperand(
364 const StaticInst *si, int idx, const MiscReg &val)
365 {
366 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
367 return thread->setMiscReg(reg_idx, val);
368 }
369
370 unsigned readStCondFailures() {
371 return thread->readStCondFailures();
372 }
373
374 void setStCondFailures(unsigned sc_failures) {
375 thread->setStCondFailures(sc_failures);
376 }
377
378 MiscReg readRegOtherThread(int regIdx, int tid = -1)
379 {
380 panic("Simple CPU models do not support multithreaded "
381 "register access.\n");
382 }
383
384 void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
385 {
386 panic("Simple CPU models do not support multithreaded "
387 "register access.\n");
388 }
389
390 //Fault CacheOp(uint8_t Op, Addr EA);
391
392#if FULL_SYSTEM
393 Fault hwrei() { return thread->hwrei(); }
394 void ev5_trap(Fault fault) { fault->invoke(tc); }
395 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
396#else
397 void syscall(int64_t callnum) { thread->syscall(callnum); }
398#endif
399
400 bool misspeculating() { return thread->misspeculating(); }
401 ThreadContext *tcBase() { return tc; }
402};
403
404#endif // __CPU_SIMPLE_BASE_HH__