1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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69namespace Trace {
70 class InstRecord;
71}
72
73
74class BaseSimpleCPU : public BaseCPU
75{
76 protected:
77 typedef TheISA::MiscReg MiscReg;
78 typedef TheISA::FloatReg FloatReg;
79 typedef TheISA::FloatRegBits FloatRegBits;
80
81 protected:
82 Trace::InstRecord *traceData;
83
84 public:

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116
117#if FULL_SYSTEM
118 Addr dbg_vtophys(Addr addr);
119
120 bool interval_stats;
121#endif
122
123 // current instruction
124 TheISA::MachInst inst;
125
126 // current extended machine instruction
127 TheISA::ExtMachInst extMachInst;
128
129 // Static data storage
130 TheISA::LargestRead dataReg;
131
132 StaticInstPtr curStaticInst;
133 StaticInstPtr curMacroStaticInst;
134
135 void checkForInterrupts();
136 Fault setupFetchRequest(Request *req);

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