base.cc (9920:028e4da64b42) base.cc (10061:3b0d0c988ed6)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
58#include "cpu/simple/base.hh"
59#include "cpu/base.hh"
60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
62#include "cpu/exetrace.hh"
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
58#include "cpu/simple/base.hh"
59#include "cpu/base.hh"
60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/pred/bpred_unit.hh"
63#include "cpu/profile.hh"
64#include "cpu/simple_thread.hh"
65#include "cpu/smt.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/thread_context.hh"
68#include "debug/Decode.hh"
69#include "debug/Fetch.hh"
70#include "debug/Quiesce.hh"

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80#include "sim/sim_object.hh"
81#include "sim/stats.hh"
82#include "sim/system.hh"
83
84using namespace std;
85using namespace TheISA;
86
87BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
64#include "cpu/profile.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/smt.hh"
67#include "cpu/static_inst.hh"
68#include "cpu/thread_context.hh"
69#include "debug/Decode.hh"
70#include "debug/Fetch.hh"
71#include "debug/Quiesce.hh"

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81#include "sim/sim_object.hh"
82#include "sim/stats.hh"
83#include "sim/system.hh"
84
85using namespace std;
86using namespace TheISA;
87
88BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
88 : BaseCPU(p), traceData(NULL), thread(NULL)
89 : BaseCPU(p),
90 branchPred(p->branchPred),
91 traceData(NULL), thread(NULL)
89{
90 if (FullSystem)
91 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
92 p->isa[0]);
93 else
94 thread = new SimpleThread(this, /* thread_num */ 0, p->system,
95 p->workload[0], p->itb, p->dtb, p->isa[0]);
96

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281 .name(name() + ".dcache_retry_cycles")
282 .desc("DCache total retry cycles")
283 .prereq(dcacheRetryCycles)
284 ;
285
286 idleFraction = constant(1.0) - notIdleFraction;
287 numIdleCycles = idleFraction * numCycles;
288 numBusyCycles = (notIdleFraction)*numCycles;
92{
93 if (FullSystem)
94 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
95 p->isa[0]);
96 else
97 thread = new SimpleThread(this, /* thread_num */ 0, p->system,
98 p->workload[0], p->itb, p->dtb, p->isa[0]);
99

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284 .name(name() + ".dcache_retry_cycles")
285 .desc("DCache total retry cycles")
286 .prereq(dcacheRetryCycles)
287 ;
288
289 idleFraction = constant(1.0) - notIdleFraction;
290 numIdleCycles = idleFraction * numCycles;
291 numBusyCycles = (notIdleFraction)*numCycles;
292
293 numBranches
294 .name(name() + ".Branches")
295 .desc("Number of branches fetched")
296 .prereq(numBranches);
297
298 numPredictedBranches
299 .name(name() + ".predictedBranches")
300 .desc("Number of branches predicted as taken")
301 .prereq(numPredictedBranches);
302
303 numBranchMispred
304 .name(name() + ".BranchMispred")
305 .desc("Number of branch mispredictions")
306 .prereq(numBranchMispred);
289}
290
291void
292BaseSimpleCPU::resetStats()
293{
294// startNumInst = numInst;
295 notIdleFraction = (_status != Idle);
296}

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429#if TRACING_ON
430 traceData = tracer->getInstRecord(curTick(), tc,
431 curStaticInst, thread->pcState(), curMacroStaticInst);
432
433 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
434 curStaticInst->getName(), curStaticInst->machInst);
435#endif // TRACING_ON
436 }
307}
308
309void
310BaseSimpleCPU::resetStats()
311{
312// startNumInst = numInst;
313 notIdleFraction = (_status != Idle);
314}

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447#if TRACING_ON
448 traceData = tracer->getInstRecord(curTick(), tc,
449 curStaticInst, thread->pcState(), curMacroStaticInst);
450
451 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
452 curStaticInst->getName(), curStaticInst->machInst);
453#endif // TRACING_ON
454 }
455
456 if (branchPred && curStaticInst && curStaticInst->isControl()) {
457 // Use a fake sequence number since we only have one
458 // instruction in flight at the same time.
459 const InstSeqNum cur_sn(0);
460 const ThreadID tid(0);
461 pred_pc = thread->pcState();
462 const bool predict_taken(
463 branchPred->predict(curStaticInst, cur_sn, pred_pc, tid));
464
465 if (predict_taken)
466 ++numPredictedBranches;
467 }
437}
438
439void
440BaseSimpleCPU::postExecute()
441{
442 assert(curStaticInst);
443
444 TheISA::PCState pc = tc->pcState();

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459 ++numLoad;
460 comLoadEventQueue[0]->serviceEvents(numLoad);
461 }
462
463 if (CPA::available()) {
464 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
465 }
466
468}
469
470void
471BaseSimpleCPU::postExecute()
472{
473 assert(curStaticInst);
474
475 TheISA::PCState pc = tc->pcState();

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490 ++numLoad;
491 comLoadEventQueue[0]->serviceEvents(numLoad);
492 }
493
494 if (CPA::available()) {
495 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
496 }
497
498 if (curStaticInst->isControl()) {
499 ++numBranches;
500 }
501
467 /* Power model statistics */
468 //integer alu accesses
469 if (curStaticInst->isInteger()){
470 numIntAluAccesses++;
471 numIntInsts++;
472 }
473
474 //float alu accesses

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502
503 if (traceData) {
504 traceData->dump();
505 delete traceData;
506 traceData = NULL;
507 }
508}
509
502 /* Power model statistics */
503 //integer alu accesses
504 if (curStaticInst->isInteger()){
505 numIntAluAccesses++;
506 numIntInsts++;
507 }
508
509 //float alu accesses

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537
538 if (traceData) {
539 traceData->dump();
540 delete traceData;
541 traceData = NULL;
542 }
543}
544
510
511void
512BaseSimpleCPU::advancePC(Fault fault)
513{
545void
546BaseSimpleCPU::advancePC(Fault fault)
547{
548 const bool branching(thread->pcState().branching());
549
514 //Since we're moving to a new pc, zero out the offset
515 fetchOffset = 0;
516 if (fault != NoFault) {
517 curMacroStaticInst = StaticInst::nullStaticInstPtr;
518 fault->invoke(tc, curStaticInst);
519 thread->decoder.reset();
520 } else {
521 if (curStaticInst) {
522 if (curStaticInst->isLastMicroop())
523 curMacroStaticInst = StaticInst::nullStaticInstPtr;
524 TheISA::PCState pcState = thread->pcState();
525 TheISA::advancePC(pcState, curStaticInst);
526 thread->pcState(pcState);
527 }
528 }
550 //Since we're moving to a new pc, zero out the offset
551 fetchOffset = 0;
552 if (fault != NoFault) {
553 curMacroStaticInst = StaticInst::nullStaticInstPtr;
554 fault->invoke(tc, curStaticInst);
555 thread->decoder.reset();
556 } else {
557 if (curStaticInst) {
558 if (curStaticInst->isLastMicroop())
559 curMacroStaticInst = StaticInst::nullStaticInstPtr;
560 TheISA::PCState pcState = thread->pcState();
561 TheISA::advancePC(pcState, curStaticInst);
562 thread->pcState(pcState);
563 }
564 }
565
566 if (branchPred && curStaticInst && curStaticInst->isControl()) {
567 // Use a fake sequence number since we only have one
568 // instruction in flight at the same time.
569 const InstSeqNum cur_sn(0);
570 const ThreadID tid(0);
571
572 if (pred_pc == thread->pcState()) {
573 // Correctly predicted branch
574 branchPred->update(cur_sn, tid);
575 } else {
576 // Mis-predicted branch
577 branchPred->squash(cur_sn, pcState(),
578 branching, tid);
579 ++numBranchMispred;
580 }
581 }
529}
530
531void
532BaseSimpleCPU::startup()
533{
534 BaseCPU::startup();
535 thread->startup();
536}
582}
583
584void
585BaseSimpleCPU::startup()
586{
587 BaseCPU::startup();
588 thread->startup();
589}