base.cc (9448:569d1e8f74e4) base.cc (9461:67a6ba6604c8)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 501 unchanged lines hidden (view full) ---

510 curMacroStaticInst = StaticInst::nullStaticInstPtr;
511 TheISA::PCState pcState = thread->pcState();
512 TheISA::advancePC(pcState, curStaticInst);
513 thread->pcState(pcState);
514 }
515 }
516}
517
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 501 unchanged lines hidden (view full) ---

510 curMacroStaticInst = StaticInst::nullStaticInstPtr;
511 TheISA::PCState pcState = thread->pcState();
512 TheISA::advancePC(pcState, curStaticInst);
513 thread->pcState(pcState);
514 }
515 }
516}
517
518void
519BaseSimpleCPU::startup()
520{
521 BaseCPU::startup();
522 thread->startup();
523}
524
518/*Fault
519BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
520{
521 // translate to physical address
522 Fault fault = NoFault;
523 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
524 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
525 if(CacheID > 1)

--- 26 unchanged lines hidden --- 		525/*Fault
526BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
527{
528 // translate to physical address
529 Fault fault = NoFault;
530 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
531 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
532 if(CacheID > 1)

--- 26 unchanged lines hidden ---