base.cc (8834:21e8d54ecf07) base.cc (8887:20ea02da9c53)
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50#include "base/cprintf.hh"
51#include "base/inifile.hh"
52#include "base/misc.hh"
53#include "base/pollevent.hh"
54#include "base/range.hh"
55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50#include "base/cprintf.hh"
51#include "base/inifile.hh"
52#include "base/misc.hh"
53#include "base/pollevent.hh"
54#include "base/range.hh"
55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
58#include "config/use_checker.hh"
59#include "cpu/simple/base.hh"
60#include "cpu/base.hh"
58#include "cpu/simple/base.hh"
59#include "cpu/base.hh"
60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/profile.hh"
63#include "cpu/simple_thread.hh"
64#include "cpu/smt.hh"
65#include "cpu/static_inst.hh"
66#include "cpu/thread_context.hh"
67#include "debug/Decode.hh"
68#include "debug/Fetch.hh"

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75#include "sim/debug.hh"
76#include "sim/faults.hh"
77#include "sim/full_system.hh"
78#include "sim/sim_events.hh"
79#include "sim/sim_object.hh"
80#include "sim/stats.hh"
81#include "sim/system.hh"
82
62#include "cpu/exetrace.hh"
63#include "cpu/profile.hh"
64#include "cpu/simple_thread.hh"
65#include "cpu/smt.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/thread_context.hh"
68#include "debug/Decode.hh"
69#include "debug/Fetch.hh"

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76#include "sim/debug.hh"
77#include "sim/faults.hh"
78#include "sim/full_system.hh"
79#include "sim/sim_events.hh"
80#include "sim/sim_object.hh"
81#include "sim/stats.hh"
82#include "sim/system.hh"
83
83#if USE_CHECKER
84#include "cpu/checker/cpu.hh"
85#include "cpu/checker/thread_context.hh"
86#endif
87
88using namespace std;
89using namespace TheISA;
90
91BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
92 : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
93{
94 if (FullSystem)
95 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
96 else
97 thread = new SimpleThread(this, /* thread_num */ 0, p->system,
98 p->workload[0], p->itb, p->dtb);
99
100 thread->setStatus(ThreadContext::Halted);
101
102 tc = thread->getTC();
103
84using namespace std;
85using namespace TheISA;
86
87BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
88 : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
89{
90 if (FullSystem)
91 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
92 else
93 thread = new SimpleThread(this, /* thread_num */ 0, p->system,
94 p->workload[0], p->itb, p->dtb);
95
96 thread->setStatus(ThreadContext::Halted);
97
98 tc = thread->getTC();
99
104#if USE_CHECKER
105 if (p->checker) {
106 BaseCPU *temp_checker = p->checker;
107 checker = dynamic_cast<CheckerCPU *>(temp_checker);
108 checker->setSystem(p->system);
109 // Manipulate thread context
110 ThreadContext *cpu_tc = tc;
111 tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
112 } else {
113 checker = NULL;
114 }
100 if (p->checker) {
101 BaseCPU *temp_checker = p->checker;
102 checker = dynamic_cast<CheckerCPU *>(temp_checker);
103 checker->setSystem(p->system);
104 // Manipulate thread context
105 ThreadContext *cpu_tc = tc;
106 tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
107 } else {
108 checker = NULL;
109 }
115#endif
116
117 numInst = 0;
118 startNumInst = 0;
119 numOp = 0;
120 startNumOp = 0;
121 numLoad = 0;
122 startNumLoad = 0;
123 lastIcacheStall = 0;

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111 numInst = 0;
112 startNumInst = 0;
113 numOp = 0;
114 startNumOp = 0;
115 numLoad = 0;
116 startNumLoad = 0;
117 lastIcacheStall = 0;

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