base.cc (8820:f39690f70bab) base.cc (8832:247fee427324)
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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341BaseSimpleCPU::setupFetchRequest(Request *req)
342{
343 Addr instAddr = thread->instAddr();
344
345 // set up memory request for instruction fetch
346 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
347
348 Addr fetchPC = (instAddr & PCMask) + fetchOffset;
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 332 unchanged lines hidden (view full) ---

341BaseSimpleCPU::setupFetchRequest(Request *req)
342{
343 Addr instAddr = thread->instAddr();
344
345 // set up memory request for instruction fetch
346 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
347
348 Addr fetchPC = (instAddr & PCMask) + fetchOffset;
349 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr);
349 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
350 instAddr);
350}
351
352
353void
354BaseSimpleCPU::preExecute()
355{
356 // maintain $r0 semantics
357 thread->setIntReg(ZeroReg, 0);

--- 195 unchanged lines hidden --- 		351}
352
353
354void
355BaseSimpleCPU::preExecute()
356{
357 // maintain $r0 semantics
358 thread->setIntReg(ZeroReg, 0);

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