base.cc (8737:770ccf3af571) base.cc (8779:2a590c51adb1)
1/*
1/*
2 * Copyright (c) 2010-2011 ARM Limited
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/faults.hh"
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/faults.hh"
44#include "arch/kernel_stats.hh"
45#include "arch/stacktrace.hh"
46#include "arch/tlb.hh"
44#include "arch/utility.hh"
47#include "arch/utility.hh"
48#include "arch/vtophys.hh"
45#include "base/loader/symtab.hh"
46#include "base/cp_annotate.hh"
47#include "base/cprintf.hh"
48#include "base/inifile.hh"
49#include "base/misc.hh"
50#include "base/pollevent.hh"
51#include "base/range.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "config/the_isa.hh"
49#include "base/loader/symtab.hh"
50#include "base/cp_annotate.hh"
51#include "base/cprintf.hh"
52#include "base/inifile.hh"
53#include "base/misc.hh"
54#include "base/pollevent.hh"
55#include "base/range.hh"
56#include "base/trace.hh"
57#include "base/types.hh"
58#include "config/the_isa.hh"
55#include "config/use_checker.hh"
56#include "cpu/simple/base.hh"
57#include "cpu/base.hh"
58#include "cpu/exetrace.hh"
59#include "cpu/profile.hh"
60#include "cpu/simple_thread.hh"
61#include "cpu/smt.hh"
62#include "cpu/static_inst.hh"
63#include "cpu/thread_context.hh"
64#include "debug/Decode.hh"
65#include "debug/Fetch.hh"
66#include "debug/Quiesce.hh"
59#include "cpu/simple/base.hh"
60#include "cpu/base.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/profile.hh"
63#include "cpu/simple_thread.hh"
64#include "cpu/smt.hh"
65#include "cpu/static_inst.hh"
66#include "cpu/thread_context.hh"
67#include "debug/Decode.hh"
68#include "debug/Fetch.hh"
69#include "debug/Quiesce.hh"
70#include "mem/mem_object.hh"
67#include "mem/packet.hh"
68#include "mem/request.hh"
69#include "params/BaseSimpleCPU.hh"
70#include "sim/byteswap.hh"
71#include "sim/debug.hh"
72#include "sim/sim_events.hh"
73#include "sim/sim_object.hh"
74#include "sim/stats.hh"
75#include "sim/system.hh"
76
71#include "mem/packet.hh"
72#include "mem/request.hh"
73#include "params/BaseSimpleCPU.hh"
74#include "sim/byteswap.hh"
75#include "sim/debug.hh"
76#include "sim/sim_events.hh"
77#include "sim/sim_object.hh"
78#include "sim/stats.hh"
79#include "sim/system.hh"
80
77#if FULL_SYSTEM
78#include "arch/kernel_stats.hh"
79#include "arch/stacktrace.hh"
80#include "arch/tlb.hh"
81#include "arch/vtophys.hh"
82#else // !FULL_SYSTEM
83#include "mem/mem_object.hh"
84#endif // FULL_SYSTEM
85
86#if USE_CHECKER
87#include "cpu/checker/cpu.hh"
88#include "cpu/checker/thread_context.hh"
89#endif
90
91using namespace std;
92using namespace TheISA;
93
94BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
95 : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
96{
97#if FULL_SYSTEM
98 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
99#else
100 thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
101 p->itb, p->dtb);
102#endif // !FULL_SYSTEM
103
104 thread->setStatus(ThreadContext::Halted);
105
106 tc = thread->getTC();
107
81using namespace std;
82using namespace TheISA;
83
84BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
85 : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
86{
87#if FULL_SYSTEM
88 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
89#else
90 thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
91 p->itb, p->dtb);
92#endif // !FULL_SYSTEM
93
94 thread->setStatus(ThreadContext::Halted);
95
96 tc = thread->getTC();
97
108#if USE_CHECKER
109 if (p->checker) {
110 BaseCPU *temp_checker = p->checker;
111 checker = dynamic_cast<CheckerCPU *>(temp_checker);
112#if FULL_SYSTEM
113 checker->setSystem(p->system);
114#endif
115 // Manipulate thread context
116 ThreadContext *cpu_tc = tc;
117 tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
118 } else {
119 checker = NULL;
120 }
121#endif
122
123 numInst = 0;
124 startNumInst = 0;
125 numLoad = 0;
126 startNumLoad = 0;
127 lastIcacheStall = 0;
128 lastDcacheStall = 0;
129
130 threadContexts.push_back(tc);
131
132
133 fetchOffset = 0;
134 stayAtPC = false;
135}
136
137BaseSimpleCPU::~BaseSimpleCPU()
138{
139}
140
141void
98 numInst = 0;
99 startNumInst = 0;
100 numLoad = 0;
101 startNumLoad = 0;
102 lastIcacheStall = 0;
103 lastDcacheStall = 0;
104
105 threadContexts.push_back(tc);
106
107
108 fetchOffset = 0;
109 stayAtPC = false;
110}
111
112BaseSimpleCPU::~BaseSimpleCPU()
113{
114}
115
116void
142BaseSimpleCPU::deallocateContext(ThreadID thread_num)
117BaseSimpleCPU::deallocateContext(int thread_num)
143{
144 // for now, these are equivalent
145 suspendContext(thread_num);
146}
147
148
149void
118{
119 // for now, these are equivalent
120 suspendContext(thread_num);
121}
122
123
124void
150BaseSimpleCPU::haltContext(ThreadID thread_num)
125BaseSimpleCPU::haltContext(int thread_num)
151{
152 // for now, these are equivalent
153 suspendContext(thread_num);
154}
155
156
157void
158BaseSimpleCPU::regStats()

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306 thread->unserialize(cp, csprintf("%s.xc.0", section));
307}
308
309void
310change_thread_state(ThreadID tid, int activate, int priority)
311{
312}
313
126{
127 // for now, these are equivalent
128 suspendContext(thread_num);
129}
130
131
132void
133BaseSimpleCPU::regStats()

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281 thread->unserialize(cp, csprintf("%s.xc.0", section));
282}
283
284void
285change_thread_state(ThreadID tid, int activate, int priority)
286{
287}
288
314#if FULL_SYSTEM
315Addr
316BaseSimpleCPU::dbg_vtophys(Addr addr)
317{
318 return vtophys(tc, addr);
319}
289Addr
290BaseSimpleCPU::dbg_vtophys(Addr addr)
291{
292 return vtophys(tc, addr);
293}
320#endif // FULL_SYSTEM
321
294
322#if FULL_SYSTEM
323void
324BaseSimpleCPU::wakeup()
325{
326 if (thread->status() != ThreadContext::Suspended)
327 return;
328
329 DPRINTF(Quiesce,"Suspended Processor awoke\n");
330 thread->activate();
331}
295void
296BaseSimpleCPU::wakeup()
297{
298 if (thread->status() != ThreadContext::Suspended)
299 return;
300
301 DPRINTF(Quiesce,"Suspended Processor awoke\n");
302 thread->activate();
303}
332#endif // FULL_SYSTEM
333
334void
335BaseSimpleCPU::checkForInterrupts()
336{
304
305void
306BaseSimpleCPU::checkForInterrupts()
307{
337#if FULL_SYSTEM
338 if (checkInterrupts(tc)) {
339 Fault interrupt = interrupts->getInterrupt(tc);
340
341 if (interrupt != NoFault) {
342 fetchOffset = 0;
343 interrupts->updateIntrInfo(tc);
344 interrupt->invoke(tc);
345 predecoder.reset();
346 }
347 }
308 if (checkInterrupts(tc)) {
309 Fault interrupt = interrupts->getInterrupt(tc);
310
311 if (interrupt != NoFault) {
312 fetchOffset = 0;
313 interrupts->updateIntrInfo(tc);
314 interrupt->invoke(tc);
315 predecoder.reset();
316 }
317 }
348#endif
349}
350
351
352void
353BaseSimpleCPU::setupFetchRequest(Request *req)
354{
355 Addr instAddr = thread->instAddr();
356

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438
439void
440BaseSimpleCPU::postExecute()
441{
442 assert(curStaticInst);
443
444 TheISA::PCState pc = tc->pcState();
445 Addr instAddr = pc.instAddr();
318}
319
320
321void
322BaseSimpleCPU::setupFetchRequest(Request *req)
323{
324 Addr instAddr = thread->instAddr();
325

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407
408void
409BaseSimpleCPU::postExecute()
410{
411 assert(curStaticInst);
412
413 TheISA::PCState pc = tc->pcState();
414 Addr instAddr = pc.instAddr();
446#if FULL_SYSTEM
447 if (thread->profile) {
448 bool usermode = TheISA::inUserMode(tc);
449 thread->profilePC = usermode ? 1 : instAddr;
450 ProfileNode *node = thread->profile->consume(tc, curStaticInst);
451 if (node)
452 thread->profileNode = node;
453 }
415 if (thread->profile) {
416 bool usermode = TheISA::inUserMode(tc);
417 thread->profilePC = usermode ? 1 : instAddr;
418 ProfileNode *node = thread->profile->consume(tc, curStaticInst);
419 if (node)
420 thread->profileNode = node;
421 }
454#endif
455
456 if (curStaticInst->isMemRef()) {
457 numMemRefs++;
458 }
459
460 if (curStaticInst->isLoad()) {
461 ++numLoad;
462 comLoadEventQueue[0]->serviceEvents(numLoad);

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423 if (curStaticInst->isMemRef()) {
424 numMemRefs++;
425 }
426
427 if (curStaticInst->isLoad()) {
428 ++numLoad;
429 comLoadEventQueue[0]->serviceEvents(numLoad);

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