base.cc (7823:dac01f14f20f) base.cc (7897:d9e8b1fd1a9f)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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137
138 BaseCPU::regStats();
139
140 numInsts
141 .name(name() + ".num_insts")
142 .desc("Number of instructions executed")
143 ;
144
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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137
138 BaseCPU::regStats();
139
140 numInsts
141 .name(name() + ".num_insts")
142 .desc("Number of instructions executed")
143 ;
144
145 numIntAluAccesses
146 .name(name() + ".num_int_alu_accesses")
147 .desc("Number of integer alu accesses")
148 ;
149
150 numFpAluAccesses
151 .name(name() + ".num_fp_alu_accesses")
152 .desc("Number of float alu accesses")
153 ;
154
155 numCallsReturns
156 .name(name() + ".num_func_calls")
157 .desc("number of times a function call or return occured")
158 ;
159
160 numCondCtrlInsts
161 .name(name() + ".num_conditional_control_insts")
162 .desc("number of instructions that are conditional controls")
163 ;
164
165 numIntInsts
166 .name(name() + ".num_int_insts")
167 .desc("number of integer instructions")
168 ;
169
170 numFpInsts
171 .name(name() + ".num_fp_insts")
172 .desc("number of float instructions")
173 ;
174
175 numIntRegReads
176 .name(name() + ".num_int_register_reads")
177 .desc("number of times the integer registers were read")
178 ;
179
180 numIntRegWrites
181 .name(name() + ".num_int_register_writes")
182 .desc("number of times the integer registers were written")
183 ;
184
185 numFpRegReads
186 .name(name() + ".num_fp_register_reads")
187 .desc("number of times the floating registers were read")
188 ;
189
190 numFpRegWrites
191 .name(name() + ".num_fp_register_writes")
192 .desc("number of times the floating registers were written")
193 ;
194
145 numMemRefs
195 numMemRefs
146 .name(name() + ".num_refs")
147 .desc("Number of memory references")
196 .name(name()+".num_mem_refs")
197 .desc("number of memory refs")
148 ;
149
198 ;
199
200 numStoreInsts
201 .name(name() + ".num_store_insts")
202 .desc("Number of store instructions")
203 ;
204
205 numLoadInsts
206 .name(name() + ".num_load_insts")
207 .desc("Number of load instructions")
208 ;
209
150 notIdleFraction
151 .name(name() + ".not_idle_fraction")
152 .desc("Percentage of non-idle cycles")
153 ;
154
155 idleFraction
156 .name(name() + ".idle_fraction")
157 .desc("Percentage of idle cycles")
158 ;
159
210 notIdleFraction
211 .name(name() + ".not_idle_fraction")
212 .desc("Percentage of non-idle cycles")
213 ;
214
215 idleFraction
216 .name(name() + ".idle_fraction")
217 .desc("Percentage of idle cycles")
218 ;
219
220 numBusyCycles
221 .name(name() + ".num_busy_cycles")
222 .desc("Number of busy cycles")
223 ;
224
225 numIdleCycles
226 .name(name()+".num_idle_cycles")
227 .desc("Number of idle cycles")
228 ;
229
160 icacheStallCycles
161 .name(name() + ".icache_stall_cycles")
162 .desc("ICache total stall cycles")
163 .prereq(icacheStallCycles)
164 ;
165
166 dcacheStallCycles
167 .name(name() + ".dcache_stall_cycles")

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177
178 dcacheRetryCycles
179 .name(name() + ".dcache_retry_cycles")
180 .desc("DCache total retry cycles")
181 .prereq(dcacheRetryCycles)
182 ;
183
184 idleFraction = constant(1.0) - notIdleFraction;
230 icacheStallCycles
231 .name(name() + ".icache_stall_cycles")
232 .desc("ICache total stall cycles")
233 .prereq(icacheStallCycles)
234 ;
235
236 dcacheStallCycles
237 .name(name() + ".dcache_stall_cycles")

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247
248 dcacheRetryCycles
249 .name(name() + ".dcache_retry_cycles")
250 .desc("DCache total retry cycles")
251 .prereq(dcacheRetryCycles)
252 ;
253
254 idleFraction = constant(1.0) - notIdleFraction;
255 numIdleCycles = idleFraction * numCycles;
256 numBusyCycles = (notIdleFraction)*numCycles;
185}
186
187void
188BaseSimpleCPU::resetStats()
189{
190// startNumInst = numInst;
191 notIdleFraction = (_status != Idle);
192}

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272 // maintain $r0 semantics
273 thread->setIntReg(ZeroReg, 0);
274#if THE_ISA == ALPHA_ISA
275 thread->setFloatReg(ZeroReg, 0.0);
276#endif // ALPHA_ISA
277
278 // check for instruction-count-based events
279 comInstEventQueue[0]->serviceEvents(numInst);
257}
258
259void
260BaseSimpleCPU::resetStats()
261{
262// startNumInst = numInst;
263 notIdleFraction = (_status != Idle);
264}

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344 // maintain $r0 semantics
345 thread->setIntReg(ZeroReg, 0);
346#if THE_ISA == ALPHA_ISA
347 thread->setFloatReg(ZeroReg, 0.0);
348#endif // ALPHA_ISA
349
350 // check for instruction-count-based events
351 comInstEventQueue[0]->serviceEvents(numInst);
352 system->instEventQueue.serviceEvents(system->totalNumInsts);
280
281 // decode the instruction
282 inst = gtoh(inst);
283
284 TheISA::PCState pcState = thread->pcState();
285
286 if (isRomMicroPC(pcState.microPC())) {
287 stayAtPC = false;

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364 ++numLoad;
365 comLoadEventQueue[0]->serviceEvents(numLoad);
366 }
367
368 if (CPA::available()) {
369 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
370 }
371
353
354 // decode the instruction
355 inst = gtoh(inst);
356
357 TheISA::PCState pcState = thread->pcState();
358
359 if (isRomMicroPC(pcState.microPC())) {
360 stayAtPC = false;

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437 ++numLoad;
438 comLoadEventQueue[0]->serviceEvents(numLoad);
439 }
440
441 if (CPA::available()) {
442 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
443 }
444
445 /* Power model statistics */
446 //integer alu accesses
447 if (curStaticInst->isInteger()){
448 numIntAluAccesses++;
449 numIntInsts++;
450 }
451
452 //float alu accesses
453 if (curStaticInst->isFloating()){
454 numFpAluAccesses++;
455 numFpInsts++;
456 }
457
458 //number of function calls/returns to get window accesses
459 if (curStaticInst->isCall() || curStaticInst->isReturn()){
460 numCallsReturns++;
461 }
462
463 //the number of branch predictions that will be made
464 if (curStaticInst->isCondCtrl()){
465 numCondCtrlInsts++;
466 }
467
468 //result bus acceses
469 if (curStaticInst->isLoad()){
470 numLoadInsts++;
471 }
472
473 if (curStaticInst->isStore()){
474 numStoreInsts++;
475 }
476 /* End power model statistics */
477
372 traceFunctions(instAddr);
373
374 if (traceData) {
375 traceData->dump();
376 delete traceData;
377 traceData = NULL;
378 }
379}

--- 56 unchanged lines hidden --- 		478 traceFunctions(instAddr);
479
480 if (traceData) {
481 traceData->dump();
482 delete traceData;
483 traceData = NULL;
484 }
485}

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