base.cc (7679:f26cc2c68b48) base.cc (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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363 }
364#endif
365}
366
367
368void
369BaseSimpleCPU::setupFetchRequest(Request *req)
370{
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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363 }
364#endif
365}
366
367
368void
369BaseSimpleCPU::setupFetchRequest(Request *req)
370{
371 Addr threadPC = thread->readPC();
371 Addr instAddr = thread->instAddr();
372
373 // set up memory request for instruction fetch
372
373 // set up memory request for instruction fetch
374#if ISA_HAS_DELAY_SLOT
375 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
376 thread->readNextPC(),thread->readNextNPC());
377#else
378 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
379 thread->readNextPC());
380#endif
374 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
381
375
382 Addr fetchPC = (threadPC & PCMask) + fetchOffset;
383 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC);
376 Addr fetchPC = (instAddr & PCMask) + fetchOffset;
377 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr);
384}
385
386
387void
388BaseSimpleCPU::preExecute()
389{
390 // maintain $r0 semantics
391 thread->setIntReg(ZeroReg, 0);
392#if THE_ISA == ALPHA_ISA
393 thread->setFloatReg(ZeroReg, 0.0);
394#endif // ALPHA_ISA
395
396 // check for instruction-count-based events
397 comInstEventQueue[0]->serviceEvents(numInst);
398
399 // decode the instruction
400 inst = gtoh(inst);
401
378}
379
380
381void
382BaseSimpleCPU::preExecute()
383{
384 // maintain $r0 semantics
385 thread->setIntReg(ZeroReg, 0);
386#if THE_ISA == ALPHA_ISA
387 thread->setFloatReg(ZeroReg, 0.0);
388#endif // ALPHA_ISA
389
390 // check for instruction-count-based events
391 comInstEventQueue[0]->serviceEvents(numInst);
392
393 // decode the instruction
394 inst = gtoh(inst);
395
402 MicroPC upc = thread->readMicroPC();
396 TheISA::PCState pcState = thread->pcState();
403
397
404 if (isRomMicroPC(upc)) {
398 if (isRomMicroPC(pcState.microPC())) {
405 stayAtPC = false;
399 stayAtPC = false;
406 curStaticInst = microcodeRom.fetchMicroop(upc, curMacroStaticInst);
400 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
401 curMacroStaticInst);
407 } else if (!curMacroStaticInst) {
408 //We're not in the middle of a macro instruction
409 StaticInstPtr instPtr = NULL;
410
411 //Predecode, ie bundle up an ExtMachInst
412 //This should go away once the constructor can be set up properly
413 predecoder.setTC(thread->getTC());
414 //If more fetch data is needed, pass it in.
402 } else if (!curMacroStaticInst) {
403 //We're not in the middle of a macro instruction
404 StaticInstPtr instPtr = NULL;
405
406 //Predecode, ie bundle up an ExtMachInst
407 //This should go away once the constructor can be set up properly
408 predecoder.setTC(thread->getTC());
409 //If more fetch data is needed, pass it in.
415 Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
410 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
416 //if(predecoder.needMoreBytes())
411 //if(predecoder.needMoreBytes())
417 predecoder.moreBytes(thread->readPC(), fetchPC, inst);
412 predecoder.moreBytes(pcState, fetchPC, inst);
418 //else
419 // predecoder.process();
420
421 //If an instruction is ready, decode it. Otherwise, we'll have to
422 //fetch beyond the MachInst at the current pc.
423 if (predecoder.extMachInstReady()) {
413 //else
414 // predecoder.process();
415
416 //If an instruction is ready, decode it. Otherwise, we'll have to
417 //fetch beyond the MachInst at the current pc.
418 if (predecoder.extMachInstReady()) {
424#if THE_ISA == X86_ISA || THE_ISA == ARM_ISA
425 thread->setNextPC(thread->readPC() + predecoder.getInstSize());
426#endif // X86_ISA
427 stayAtPC = false;
419 stayAtPC = false;
428 instPtr = StaticInst::decode(predecoder.getExtMachInst(),
429 thread->readPC());
420 ExtMachInst machInst = predecoder.getExtMachInst(pcState);
421 thread->pcState(pcState);
422 instPtr = StaticInst::decode(machInst, pcState.instAddr());
430 } else {
431 stayAtPC = true;
432 fetchOffset += sizeof(MachInst);
433 }
434
435 //If we decoded an instruction and it's microcoded, start pulling
436 //out micro ops
437 if (instPtr && instPtr->isMacroop()) {
438 curMacroStaticInst = instPtr;
423 } else {
424 stayAtPC = true;
425 fetchOffset += sizeof(MachInst);
426 }
427
428 //If we decoded an instruction and it's microcoded, start pulling
429 //out micro ops
430 if (instPtr && instPtr->isMacroop()) {
431 curMacroStaticInst = instPtr;
439 curStaticInst = curMacroStaticInst->fetchMicroop(upc);
432 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
440 } else {
441 curStaticInst = instPtr;
442 }
443 } else {
444 //Read the next micro op from the macro op
433 } else {
434 curStaticInst = instPtr;
435 }
436 } else {
437 //Read the next micro op from the macro op
445 curStaticInst = curMacroStaticInst->fetchMicroop(upc);
438 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
446 }
447
448 //If we decoded an instruction this "tick", record information about it.
449 if(curStaticInst)
450 {
451#if TRACING_ON
452 traceData = tracer->getInstRecord(curTick, tc,
439 }
440
441 //If we decoded an instruction this "tick", record information about it.
442 if(curStaticInst)
443 {
444#if TRACING_ON
445 traceData = tracer->getInstRecord(curTick, tc,
453 curStaticInst, thread->readPC(),
454 curMacroStaticInst, thread->readMicroPC());
446 curStaticInst, thread->pcState(), curMacroStaticInst);
455
456 DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
457 curStaticInst->getName(), curStaticInst->machInst);
458#endif // TRACING_ON
459 }
460}
461
462void
463BaseSimpleCPU::postExecute()
464{
447
448 DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
449 curStaticInst->getName(), curStaticInst->machInst);
450#endif // TRACING_ON
451 }
452}
453
454void
455BaseSimpleCPU::postExecute()
456{
457 assert(curStaticInst);
458
459 TheISA::PCState pc = tc->pcState();
460 Addr instAddr = pc.instAddr();
465#if FULL_SYSTEM
461#if FULL_SYSTEM
466 if (thread->profile && curStaticInst) {
462 if (thread->profile) {
467 bool usermode = TheISA::inUserMode(tc);
463 bool usermode = TheISA::inUserMode(tc);
468 thread->profilePC = usermode ? 1 : thread->readPC();
464 thread->profilePC = usermode ? 1 : instAddr;
469 ProfileNode *node = thread->profile->consume(tc, curStaticInst);
470 if (node)
471 thread->profileNode = node;
472 }
473#endif
474
475 if (curStaticInst->isMemRef()) {
476 numMemRefs++;
477 }
478
479 if (curStaticInst->isLoad()) {
480 ++numLoad;
481 comLoadEventQueue[0]->serviceEvents(numLoad);
482 }
483
484 if (CPA::available()) {
465 ProfileNode *node = thread->profile->consume(tc, curStaticInst);
466 if (node)
467 thread->profileNode = node;
468 }
469#endif
470
471 if (curStaticInst->isMemRef()) {
472 numMemRefs++;
473 }
474
475 if (curStaticInst->isLoad()) {
476 ++numLoad;
477 comLoadEventQueue[0]->serviceEvents(numLoad);
478 }
479
480 if (CPA::available()) {
485 CPA::cpa()->swAutoBegin(tc, thread->readNextPC());
481 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
486 }
487
482 }
483
488 traceFunctions(thread->readPC());
484 traceFunctions(instAddr);
489
490 if (traceData) {
491 traceData->dump();
492 delete traceData;
493 traceData = NULL;
494 }
495}
496
497
498void
499BaseSimpleCPU::advancePC(Fault fault)
500{
501 //Since we're moving to a new pc, zero out the offset
502 fetchOffset = 0;
503 if (fault != NoFault) {
504 curMacroStaticInst = StaticInst::nullStaticInstPtr;
505 fault->invoke(tc, curStaticInst);
506 predecoder.reset();
507 } else {
485
486 if (traceData) {
487 traceData->dump();
488 delete traceData;
489 traceData = NULL;
490 }
491}
492
493
494void
495BaseSimpleCPU::advancePC(Fault fault)
496{
497 //Since we're moving to a new pc, zero out the offset
498 fetchOffset = 0;
499 if (fault != NoFault) {
500 curMacroStaticInst = StaticInst::nullStaticInstPtr;
501 fault->invoke(tc, curStaticInst);
502 predecoder.reset();
503 } else {
508 //If we're at the last micro op for this instruction
509 if (curStaticInst && curStaticInst->isLastMicroop()) {
510 //We should be working with a macro op or be in the ROM
511 assert(curMacroStaticInst ||
512 isRomMicroPC(thread->readMicroPC()));
513 //Close out this macro op, and clean up the
514 //microcode state
515 curMacroStaticInst = StaticInst::nullStaticInstPtr;
516 thread->setMicroPC(normalMicroPC(0));
517 thread->setNextMicroPC(normalMicroPC(1));
504 if (curStaticInst) {
505 if (curStaticInst->isLastMicroop())
506 curMacroStaticInst = StaticInst::nullStaticInstPtr;
507 TheISA::PCState pcState = thread->pcState();
508 TheISA::advancePC(pcState, curStaticInst);
509 thread->pcState(pcState);
518 }
510 }
519 //If we're still in a macro op
520 if (curMacroStaticInst || isRomMicroPC(thread->readMicroPC())) {
521 //Advance the micro pc
522 thread->setMicroPC(thread->readNextMicroPC());
523 //Advance the "next" micro pc. Note that there are no delay
524 //slots, and micro ops are "word" addressed.
525 thread->setNextMicroPC(thread->readNextMicroPC() + 1);
526 } else {
527 // go to the next instruction
528 thread->setPC(thread->readNextPC());
529 thread->setNextPC(thread->readNextNPC());
530 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
531 assert(thread->readNextPC() != thread->readNextNPC());
532 }
533 }
534}
535
536/*Fault
537BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
538{
539 // translate to physical address
540 Fault fault = NoFault;

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512}
513
514/*Fault
515BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
516{
517 // translate to physical address
518 Fault fault = NoFault;

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