base.cc (7100:3467916569e3) base.cc (7338:0d6c08d25fe7)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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341BaseSimpleCPU::checkForInterrupts()
342{
343#if FULL_SYSTEM
344 if (checkInterrupts(tc)) {
345 Fault interrupt = interrupts->getInterrupt(tc);
346
347 if (interrupt != NoFault) {
348 predecoder.reset();
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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353BaseSimpleCPU::checkForInterrupts()
354{
355#if FULL_SYSTEM
356 if (checkInterrupts(tc)) {
357 Fault interrupt = interrupts->getInterrupt(tc);
358
359 if (interrupt != NoFault) {
360 predecoder.reset();
361 fetchOffset = 0;
349 interrupts->updateIntrInfo(tc);
350 interrupt->invoke(tc);
351 }
352 }
353#endif
354}
355
356

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362 interrupts->updateIntrInfo(tc);
363 interrupt->invoke(tc);
364 }
365 }
366#endif
367}
368
369

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