base.cc (6029:007c36616f47) base.cc (6105:a27c0934de24)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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43#include "cpu/exetrace.hh"
44#include "cpu/profile.hh"
45#include "cpu/simple/base.hh"
46#include "cpu/simple_thread.hh"
47#include "cpu/smt.hh"
48#include "cpu/static_inst.hh"
49#include "cpu/thread_context.hh"
50#include "mem/packet.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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43#include "cpu/exetrace.hh"
44#include "cpu/profile.hh"
45#include "cpu/simple/base.hh"
46#include "cpu/simple_thread.hh"
47#include "cpu/smt.hh"
48#include "cpu/static_inst.hh"
49#include "cpu/thread_context.hh"
50#include "mem/packet.hh"
51#include "mem/request.hh"
51#include "sim/byteswap.hh"
52#include "sim/debug.hh"
53#include "sim/host.hh"
54#include "sim/sim_events.hh"
55#include "sim/sim_object.hh"
56#include "sim/stats.hh"
57#include "sim/system.hh"
58

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275 thread->mem->write(memReq, data);
276 if (dcacheInterface) {
277 memReq->cmd = Copy;
278 memReq->completionEvent = NULL;
279 memReq->paddr = thread->copySrcPhysAddr;
280 memReq->dest = dest_addr;
281 memReq->size = 64;
282 memReq->time = curTick;
52#include "sim/byteswap.hh"
53#include "sim/debug.hh"
54#include "sim/host.hh"
55#include "sim/sim_events.hh"
56#include "sim/sim_object.hh"
57#include "sim/stats.hh"
58#include "sim/system.hh"
59

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276 thread->mem->write(memReq, data);
277 if (dcacheInterface) {
278 memReq->cmd = Copy;
279 memReq->completionEvent = NULL;
280 memReq->paddr = thread->copySrcPhysAddr;
281 memReq->dest = dest_addr;
282 memReq->size = 64;
283 memReq->time = curTick;
283 memReq->flags &= ~INST_READ;
284 memReq->flags &= ~INST_FETCH;
284 dcacheInterface->access(memReq);
285 }
286 }
287 else
288 assert(!fault->isAlignmentFault());
289
290 return fault;
291#else

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341 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
342 thread->readNextPC(),thread->readNextNPC());
343#else
344 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
345 thread->readNextPC());
346#endif
347
348 Addr fetchPC = (threadPC & PCMask) + fetchOffset;
285 dcacheInterface->access(memReq);
286 }
287 }
288 else
289 assert(!fault->isAlignmentFault());
290
291 return fault;
292#else

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342 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
343 thread->readNextPC(),thread->readNextNPC());
344#else
345 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
346 thread->readNextPC());
347#endif
348
349 Addr fetchPC = (threadPC & PCMask) + fetchOffset;
349 req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
350 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC);
350}
351
352
353void
354BaseSimpleCPU::preExecute()
355{
356 // maintain $r0 semantics
357 thread->setIntReg(ZeroReg, 0);

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352
353
354void
355BaseSimpleCPU::preExecute()
356{
357 // maintain $r0 semantics
358 thread->setIntReg(ZeroReg, 0);

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