base.cc (5891:73084c6bb183) base.cc (5894:8091ac99341a)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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325 interrupts->updateIntrInfo(tc);
326 interrupt->invoke(tc);
327 }
328 }
329#endif
330}
331
332
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 316 unchanged lines hidden (view full) ---

325 interrupts->updateIntrInfo(tc);
326 interrupt->invoke(tc);
327 }
328 }
329#endif
330}
331
332
333Fault
333void
334BaseSimpleCPU::setupFetchRequest(Request *req)
335{
336 Addr threadPC = thread->readPC();
337
338 // set up memory request for instruction fetch
339#if ISA_HAS_DELAY_SLOT
340 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
341 thread->readNextPC(),thread->readNextNPC());
342#else
343 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
344 thread->readNextPC());
345#endif
346
347 Addr fetchPC = (threadPC & PCMask) + fetchOffset;
348 req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
334BaseSimpleCPU::setupFetchRequest(Request *req)
335{
336 Addr threadPC = thread->readPC();
337
338 // set up memory request for instruction fetch
339#if ISA_HAS_DELAY_SLOT
340 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
341 thread->readNextPC(),thread->readNextNPC());
342#else
343 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
344 thread->readNextPC());
345#endif
346
347 Addr fetchPC = (threadPC & PCMask) + fetchOffset;
348 req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
349
350 Fault fault = thread->itb->translateAtomic(req, tc);
351
352 return fault;
353}
354
355
356void
357BaseSimpleCPU::preExecute()
358{
359 // maintain $r0 semantics
360 thread->setIntReg(ZeroReg, 0);

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350
351
352void
353BaseSimpleCPU::preExecute()
354{
355 // maintain $r0 semantics
356 thread->setIntReg(ZeroReg, 0);

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