base.cc (4510:98339396410c) base.cc (4514:ac9b34438d34)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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324 }
325#endif
326}
327
328
329Fault
330BaseSimpleCPU::setupFetchRequest(Request *req)
331{
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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324 }
325#endif
326}
327
328
329Fault
330BaseSimpleCPU::setupFetchRequest(Request *req)
331{
332 uint64_t threadPC = thread->readPC();
332 Addr threadPC = thread->readPC();
333
334 // set up memory request for instruction fetch
335#if ISA_HAS_DELAY_SLOT
336 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
337 thread->readNextPC(),thread->readNextNPC());
338#else
339 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",threadPC,
340 thread->readNextPC());
341#endif
342
333
334 // set up memory request for instruction fetch
335#if ISA_HAS_DELAY_SLOT
336 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
337 thread->readNextPC(),thread->readNextNPC());
338#else
339 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",threadPC,
340 thread->readNextPC());
341#endif
342
343 const Addr PCMask = ~(sizeof(MachInst) - 1);
344 Addr fetchPC = thread->readPC() + fetchOffset;
343 const Addr PCMask = ~((Addr)sizeof(MachInst) - 1);
344 Addr fetchPC = threadPC + fetchOffset;
345 req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, threadPC);
346
347 Fault fault = thread->translateInstReq(req);
348
349 return fault;
350}
351
352

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375 if (!curMacroStaticInst) {
376
377 StaticInstPtr instPtr = NULL;
378
379 //Predecode, ie bundle up an ExtMachInst
380 //This should go away once the constructor can be set up properly
381 predecoder.setTC(thread->getTC());
382 //If more fetch data is needed, pass it in.
345 req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, threadPC);
346
347 Fault fault = thread->translateInstReq(req);
348
349 return fault;
350}
351
352

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375 if (!curMacroStaticInst) {
376
377 StaticInstPtr instPtr = NULL;
378
379 //Predecode, ie bundle up an ExtMachInst
380 //This should go away once the constructor can be set up properly
381 predecoder.setTC(thread->getTC());
382 //If more fetch data is needed, pass it in.
383 const Addr PCMask = ~(sizeof(MachInst) - 1);
383 const Addr PCMask = ~((Addr)sizeof(MachInst) - 1);
384 if(predecoder.needMoreBytes())
385 predecoder.moreBytes((thread->readPC() & PCMask) + fetchOffset,
386 0, inst);
387 else
388 predecoder.process();
389
390 //If an instruction is ready, decode it. Otherwise, we'll have to
391 //fetch beyond the MachInst at the current pc.

--- 122 unchanged lines hidden --- 		384 if(predecoder.needMoreBytes())
385 predecoder.moreBytes((thread->readPC() & PCMask) + fetchOffset,
386 0, inst);
387 else
388 predecoder.process();
389
390 //If an instruction is ready, decode it. Otherwise, we'll have to
391 //fetch beyond the MachInst at the current pc.

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