base.cc (3484:9b7ac1654430) base.cc (3520:4f4a2054fd85)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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307}
308#endif // FULL_SYSTEM
309
310void
311BaseSimpleCPU::checkForInterrupts()
312{
313#if FULL_SYSTEM
314 if (checkInterrupts && check_interrupts() && !thread->inPalMode()) {
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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307}
308#endif // FULL_SYSTEM
309
310void
311BaseSimpleCPU::checkForInterrupts()
312{
313#if FULL_SYSTEM
314 if (checkInterrupts && check_interrupts() && !thread->inPalMode()) {
315 int ipl = 0;
316 int summary = 0;
317 checkInterrupts = false;
315 checkInterrupts = false;
316 Fault interrupt = interrupts.getInterrupt(tc);
318
317
319 if (thread->readMiscReg(IPR_SIRR)) {
320 for (int i = INTLEVEL_SOFTWARE_MIN;
321 i < INTLEVEL_SOFTWARE_MAX; i++) {
322 if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
323 // See table 4-19 of 21164 hardware reference
324 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
325 summary |= (ULL(1) << i);
326 }
327 }
318 if (interrupt != NoFault) {
319 interrupt->invoke(tc);
328 }
320 }
329
330 uint64_t interrupts = thread->cpu->intr_status();
331 for (int i = INTLEVEL_EXTERNAL_MIN;
332 i < INTLEVEL_EXTERNAL_MAX; i++) {
333 if (interrupts & (ULL(1) << i)) {
334 // See table 4-19 of 21164 hardware reference
335 ipl = i;
336 summary |= (ULL(1) << i);
337 }
338 }
339
340 if (thread->readMiscReg(IPR_ASTRR))
341 panic("asynchronous traps not implemented\n");
342
343 if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
344 thread->setMiscReg(IPR_ISR, summary);
345 thread->setMiscReg(IPR_INTID, ipl);
346
347 Fault(new InterruptFault)->invoke(tc);
348
349 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
350 thread->readMiscReg(IPR_IPLR), ipl, summary);
351 }
352 }
353#endif
354}
355
356
357Fault
358BaseSimpleCPU::setupFetchRequest(Request *req)
359{

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322#endif
323}
324
325
326Fault
327BaseSimpleCPU::setupFetchRequest(Request *req)
328{

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