base.cc (3280:91bfa4f79c53) base.cc (3348:11f6ef023158)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 33 unchanged lines hidden (view full) ---

42#include "cpu/exetrace.hh"
43#include "cpu/profile.hh"
44#include "cpu/simple/base.hh"
45#include "cpu/simple_thread.hh"
46#include "cpu/smt.hh"
47#include "cpu/static_inst.hh"
48#include "cpu/thread_context.hh"
49#include "kern/kernel_stats.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 33 unchanged lines hidden (view full) ---

42#include "cpu/exetrace.hh"
43#include "cpu/profile.hh"
44#include "cpu/simple/base.hh"
45#include "cpu/simple_thread.hh"
46#include "cpu/smt.hh"
47#include "cpu/static_inst.hh"
48#include "cpu/thread_context.hh"
49#include "kern/kernel_stats.hh"
50#include "mem/packet_impl.hh"
50#include "mem/packet.hh"
51#include "sim/builder.hh"
52#include "sim/byteswap.hh"
53#include "sim/debug.hh"
54#include "sim/host.hh"
55#include "sim/sim_events.hh"
56#include "sim/sim_object.hh"
57#include "sim/stats.hh"
58#include "sim/system.hh"

--- 332 unchanged lines hidden (view full) ---

391
392 thread->funcExeInst++;
393
394 // check for instruction-count-based events
395 comInstEventQueue[0]->serviceEvents(numInst);
396
397 // decode the instruction
398 inst = gtoh(inst);
51#include "sim/builder.hh"
52#include "sim/byteswap.hh"
53#include "sim/debug.hh"
54#include "sim/host.hh"
55#include "sim/sim_events.hh"
56#include "sim/sim_object.hh"
57#include "sim/stats.hh"
58#include "sim/system.hh"

--- 332 unchanged lines hidden (view full) ---

391
392 thread->funcExeInst++;
393
394 // check for instruction-count-based events
395 comInstEventQueue[0]->serviceEvents(numInst);
396
397 // decode the instruction
398 inst = gtoh(inst);
399 //If we're not in the middle of a macro instruction
400 if (!curMacroStaticInst) {
401 StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
402 if (instPtr->isMacroOp()) {
403 curMacroStaticInst = instPtr;
404 curStaticInst = curMacroStaticInst->fetchMicroOp(0);
405 } else {
406 curStaticInst = instPtr;
407 }
408 } else {
409 //Read the next micro op from the macro op
410 curStaticInst = curMacroStaticInst->fetchMicroOp(thread->readMicroPC());
411 }
399 curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC()));
412
400
413
414 traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
415 thread->readPC());
416
417 DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
418 curStaticInst->getName(), curStaticInst->getOpcode(),
419 curStaticInst->machInst);
420
421#if FULL_SYSTEM

--- 32 unchanged lines hidden (view full) ---

454}
455
456
457void
458BaseSimpleCPU::advancePC(Fault fault)
459{
460 if (fault != NoFault) {
461 fault->invoke(tc);
401 traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
402 thread->readPC());
403
404 DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
405 curStaticInst->getName(), curStaticInst->getOpcode(),
406 curStaticInst->machInst);
407
408#if FULL_SYSTEM

--- 32 unchanged lines hidden (view full) ---

441}
442
443
444void
445BaseSimpleCPU::advancePC(Fault fault)
446{
447 if (fault != NoFault) {
448 fault->invoke(tc);
462 } else {
463 //If we're at the last micro op for this instruction
464 if (curStaticInst->isLastMicroOp()) {
465 //We should be working with a macro op
466 assert(curMacroStaticInst);
467 //Close out this macro op, and clean up the
468 //microcode state
469 curMacroStaticInst = StaticInst::nullStaticInstPtr;
470 thread->setMicroPC(0);
471 thread->setNextMicroPC(1);
472 }
473 //If we're still in a macro op
474 if (curMacroStaticInst) {
475 //Advance the micro pc
476 thread->setMicroPC(thread->readNextMicroPC());
477 //Advance the "next" micro pc. Note that there are no delay
478 //slots, and micro ops are "word" addressed.
479 thread->setNextMicroPC(thread->readNextMicroPC() + 1);
480 } else {
481 // go to the next instruction
482 thread->setPC(thread->readNextPC());
449 }
450 else {
451 // go to the next instruction
452 thread->setPC(thread->readNextPC());
483#if ISA_HAS_DELAY_SLOT
453#if ISA_HAS_DELAY_SLOT
484 thread->setNextPC(thread->readNextNPC());
485 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
486 assert(thread->readNextPC() != thread->readNextNPC());
454 thread->setNextPC(thread->readNextNPC());
455 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
456 assert(thread->readNextPC() != thread->readNextNPC());
487#else
457#else
488 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
458 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
489#endif
459#endif
490 }
460
491 }
492
493#if FULL_SYSTEM
494 Addr oldpc;
495 do {
496 oldpc = thread->readPC();
497 system->pcEventQueue.service(tc);
498 } while (oldpc != thread->readPC());
499#endif
500}
501
461 }
462
463#if FULL_SYSTEM
464 Addr oldpc;
465 do {
466 oldpc = thread->readPC();
467 system->pcEventQueue.service(tc);
468 } while (oldpc != thread->readPC());
469#endif
470}
471