base.cc (10905:a6ca6831e775) base.cc (11147:cc8d6e99cf46)
1/*
1/*
2 * Copyright (c) 2010-2012 ARM Limited
2 * Copyright (c) 2010-2012,2015 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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57#include "config/the_isa.hh"
58#include "cpu/simple/base.hh"
59#include "cpu/base.hh"
60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/pred/bpred_unit.hh"
64#include "cpu/profile.hh"
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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57#include "config/the_isa.hh"
58#include "cpu/simple/base.hh"
59#include "cpu/base.hh"
60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/pred/bpred_unit.hh"
64#include "cpu/profile.hh"
65#include "cpu/simple/exec_context.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/smt.hh"
67#include "cpu/static_inst.hh"
68#include "cpu/thread_context.hh"
69#include "debug/Decode.hh"
70#include "debug/Fetch.hh"
71#include "debug/Quiesce.hh"
72#include "mem/mem_object.hh"

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82#include "sim/stats.hh"
83#include "sim/system.hh"
84
85using namespace std;
86using namespace TheISA;
87
88BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
89 : BaseCPU(p),
66#include "cpu/simple_thread.hh"
67#include "cpu/smt.hh"
68#include "cpu/static_inst.hh"
69#include "cpu/thread_context.hh"
70#include "debug/Decode.hh"
71#include "debug/Fetch.hh"
72#include "debug/Quiesce.hh"
73#include "mem/mem_object.hh"

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83#include "sim/stats.hh"
84#include "sim/system.hh"
85
86using namespace std;
87using namespace TheISA;
88
89BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
90 : BaseCPU(p),
91 curThread(0),
90 branchPred(p->branchPred),
92 branchPred(p->branchPred),
91 traceData(NULL), thread(NULL), _status(Idle), interval_stats(false),
92 inst()
93 traceData(NULL),
94 inst(),
95 _status(Idle)
93{
96{
94 if (FullSystem)
95 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
96 p->isa[0]);
97 else
98 thread = new SimpleThread(this, /* thread_num */ 0, p->system,
99 p->workload[0], p->itb, p->dtb, p->isa[0]);
97 SimpleThread *thread;
100
98
101 thread->setStatus(ThreadContext::Halted);
99 for (unsigned i = 0; i < numThreads; i++) {
100 if (FullSystem) {
101 thread = new SimpleThread(this, i, p->system,
102 p->itb, p->dtb, p->isa[i]);
103 } else {
104 thread = new SimpleThread(this, i, p->system, p->workload[i],
105 p->itb, p->dtb, p->isa[i]);
106 }
107 threadInfo.push_back(new SimpleExecContext(this, thread));
108 ThreadContext *tc = thread->getTC();
109 threadContexts.push_back(tc);
110 }
102
111
103 tc = thread->getTC();
104
105 if (p->checker) {
112 if (p->checker) {
113 if (numThreads != 1)
114 fatal("Checker currently does not support SMT");
115
106 BaseCPU *temp_checker = p->checker;
107 checker = dynamic_cast<CheckerCPU *>(temp_checker);
108 checker->setSystem(p->system);
109 // Manipulate thread context
116 BaseCPU *temp_checker = p->checker;
117 checker = dynamic_cast<CheckerCPU *>(temp_checker);
118 checker->setSystem(p->system);
119 // Manipulate thread context
110 ThreadContext *cpu_tc = tc;
111 tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
120 ThreadContext *cpu_tc = threadContexts[0];
121 threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
112 } else {
113 checker = NULL;
114 }
122 } else {
123 checker = NULL;
124 }
125}
115
126
116 numInst = 0;
117 startNumInst = 0;
118 numOp = 0;
119 startNumOp = 0;
120 numLoad = 0;
121 startNumLoad = 0;
122 lastIcacheStall = 0;
123 lastDcacheStall = 0;
127void
128BaseSimpleCPU::init()
129{
130 BaseCPU::init();
124
131
125 threadContexts.push_back(tc);
132 for (auto tc : threadContexts) {
133 // Initialise the ThreadContext's memory proxies
134 tc->initMemProxies(tc);
126
135
136 if (FullSystem && !params()->switched_out) {
137 // initialize CPU, including PC
138 TheISA::initCPU(tc, tc->contextId());
139 }
140 }
141}
127
142
128 fetchOffset = 0;
129 stayAtPC = false;
143void
144BaseSimpleCPU::checkPcEventQueue()
145{
146 Addr oldpc, pc = threadInfo[curThread]->thread->instAddr();
147 do {
148 oldpc = pc;
149 system->pcEventQueue.service(threadContexts[curThread]);
150 pc = threadInfo[curThread]->thread->instAddr();
151 } while (oldpc != pc);
130}
131
152}
153
154void
155BaseSimpleCPU::swapActiveThread()
156{
157 if (numThreads > 1) {
158 if ((!curStaticInst || !curStaticInst->isDelayedCommit()) &&
159 !threadInfo[curThread]->stayAtPC) {
160 // Swap active threads
161 if (!activeThreads.empty()) {
162 curThread = activeThreads.front();
163 activeThreads.pop_front();
164 activeThreads.push_back(curThread);
165 }
166 }
167 }
168}
169
170void
171BaseSimpleCPU::countInst()
172{
173 SimpleExecContext& t_info = *threadInfo[curThread];
174
175 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
176 t_info.numInst++;
177 t_info.numInsts++;
178 }
179 t_info.numOp++;
180 t_info.numOps++;
181
182 system->totalNumInsts++;
183 t_info.thread->funcExeInst++;
184}
185
186Counter
187BaseSimpleCPU::totalInsts() const
188{
189 Counter total_inst = 0;
190 for (auto& t_info : threadInfo) {
191 total_inst += t_info->numInst;
192 }
193
194 return total_inst;
195}
196
197Counter
198BaseSimpleCPU::totalOps() const
199{
200 Counter total_op = 0;
201 for (auto& t_info : threadInfo) {
202 total_op += t_info->numOp;
203 }
204
205 return total_op;
206}
207
132BaseSimpleCPU::~BaseSimpleCPU()
133{
134}
135
136void
137BaseSimpleCPU::haltContext(ThreadID thread_num)
138{
139 // for now, these are equivalent
140 suspendContext(thread_num);
141}
142
143
144void
145BaseSimpleCPU::regStats()
146{
147 using namespace Stats;
148
149 BaseCPU::regStats();
150
208BaseSimpleCPU::~BaseSimpleCPU()
209{
210}
211
212void
213BaseSimpleCPU::haltContext(ThreadID thread_num)
214{
215 // for now, these are equivalent
216 suspendContext(thread_num);
217}
218
219
220void
221BaseSimpleCPU::regStats()
222{
223 using namespace Stats;
224
225 BaseCPU::regStats();
226
151 numInsts
152 .name(name() + ".committedInsts")
153 .desc("Number of instructions committed")
154 ;
227 for (ThreadID tid = 0; tid < numThreads; tid++) {
228 SimpleExecContext& t_info = *threadInfo[tid];
155
229
156 numOps
157 .name(name() + ".committedOps")
158 .desc("Number of ops (including micro ops) committed")
159 ;
230 std::string thread_str = name();
231 if (numThreads > 1)
232 thread_str += ".thread" + std::to_string(tid);
160
233
161 numIntAluAccesses
162 .name(name() + ".num_int_alu_accesses")
163 .desc("Number of integer alu accesses")
164 ;
234 t_info.numInsts
235 .name(thread_str + ".committedInsts")
236 .desc("Number of instructions committed")
237 ;
165
238
166 numFpAluAccesses
167 .name(name() + ".num_fp_alu_accesses")
168 .desc("Number of float alu accesses")
169 ;
239 t_info.numOps
240 .name(thread_str + ".committedOps")
241 .desc("Number of ops (including micro ops) committed")
242 ;
170
243
171 numCallsReturns
172 .name(name() + ".num_func_calls")
173 .desc("number of times a function call or return occured")
174 ;
244 t_info.numIntAluAccesses
245 .name(thread_str + ".num_int_alu_accesses")
246 .desc("Number of integer alu accesses")
247 ;
175
248
176 numCondCtrlInsts
177 .name(name() + ".num_conditional_control_insts")
178 .desc("number of instructions that are conditional controls")
179 ;
249 t_info.numFpAluAccesses
250 .name(thread_str + ".num_fp_alu_accesses")
251 .desc("Number of float alu accesses")
252 ;
180
253
181 numIntInsts
182 .name(name() + ".num_int_insts")
183 .desc("number of integer instructions")
184 ;
254 t_info.numCallsReturns
255 .name(thread_str + ".num_func_calls")
256 .desc("number of times a function call or return occured")
257 ;
185
258
186 numFpInsts
187 .name(name() + ".num_fp_insts")
188 .desc("number of float instructions")
189 ;
259 t_info.numCondCtrlInsts
260 .name(thread_str + ".num_conditional_control_insts")
261 .desc("number of instructions that are conditional controls")
262 ;
190
263
191 numIntRegReads
192 .name(name() + ".num_int_register_reads")
193 .desc("number of times the integer registers were read")
194 ;
264 t_info.numIntInsts
265 .name(thread_str + ".num_int_insts")
266 .desc("number of integer instructions")
267 ;
195
268
196 numIntRegWrites
197 .name(name() + ".num_int_register_writes")
198 .desc("number of times the integer registers were written")
199 ;
269 t_info.numFpInsts
270 .name(thread_str + ".num_fp_insts")
271 .desc("number of float instructions")
272 ;
200
273
201 numFpRegReads
202 .name(name() + ".num_fp_register_reads")
203 .desc("number of times the floating registers were read")
204 ;
274 t_info.numIntRegReads
275 .name(thread_str + ".num_int_register_reads")
276 .desc("number of times the integer registers were read")
277 ;
205
278
206 numFpRegWrites
207 .name(name() + ".num_fp_register_writes")
208 .desc("number of times the floating registers were written")
209 ;
279 t_info.numIntRegWrites
280 .name(thread_str + ".num_int_register_writes")
281 .desc("number of times the integer registers were written")
282 ;
210
283
211 numCCRegReads
212 .name(name() + ".num_cc_register_reads")
213 .desc("number of times the CC registers were read")
214 .flags(nozero)
215 ;
284 t_info.numFpRegReads
285 .name(thread_str + ".num_fp_register_reads")
286 .desc("number of times the floating registers were read")
287 ;
216
288
217 numCCRegWrites
218 .name(name() + ".num_cc_register_writes")
219 .desc("number of times the CC registers were written")
220 .flags(nozero)
221 ;
289 t_info.numFpRegWrites
290 .name(thread_str + ".num_fp_register_writes")
291 .desc("number of times the floating registers were written")
292 ;
222
293
223 numMemRefs
224 .name(name()+".num_mem_refs")
225 .desc("number of memory refs")
226 ;
294 t_info.numCCRegReads
295 .name(thread_str + ".num_cc_register_reads")
296 .desc("number of times the CC registers were read")
297 .flags(nozero)
298 ;
227
299
228 numStoreInsts
229 .name(name() + ".num_store_insts")
230 .desc("Number of store instructions")
231 ;
300 t_info.numCCRegWrites
301 .name(thread_str + ".num_cc_register_writes")
302 .desc("number of times the CC registers were written")
303 .flags(nozero)
304 ;
232
305
233 numLoadInsts
234 .name(name() + ".num_load_insts")
235 .desc("Number of load instructions")
236 ;
306 t_info.numMemRefs
307 .name(thread_str + ".num_mem_refs")
308 .desc("number of memory refs")
309 ;
237
310
238 notIdleFraction
239 .name(name() + ".not_idle_fraction")
240 .desc("Percentage of non-idle cycles")
241 ;
311 t_info.numStoreInsts
312 .name(thread_str + ".num_store_insts")
313 .desc("Number of store instructions")
314 ;
242
315
243 idleFraction
244 .name(name() + ".idle_fraction")
245 .desc("Percentage of idle cycles")
246 ;
316 t_info.numLoadInsts
317 .name(thread_str + ".num_load_insts")
318 .desc("Number of load instructions")
319 ;
247
320
248 numBusyCycles
249 .name(name() + ".num_busy_cycles")
250 .desc("Number of busy cycles")
251 ;
321 t_info.notIdleFraction
322 .name(thread_str + ".not_idle_fraction")
323 .desc("Percentage of non-idle cycles")
324 ;
252
325
253 numIdleCycles
254 .name(name()+".num_idle_cycles")
255 .desc("Number of idle cycles")
256 ;
326 t_info.idleFraction
327 .name(thread_str + ".idle_fraction")
328 .desc("Percentage of idle cycles")
329 ;
257
330
258 icacheStallCycles
259 .name(name() + ".icache_stall_cycles")
260 .desc("ICache total stall cycles")
261 .prereq(icacheStallCycles)
262 ;
331 t_info.numBusyCycles
332 .name(thread_str + ".num_busy_cycles")
333 .desc("Number of busy cycles")
334 ;
263
335
264 dcacheStallCycles
265 .name(name() + ".dcache_stall_cycles")
266 .desc("DCache total stall cycles")
267 .prereq(dcacheStallCycles)
268 ;
336 t_info.numIdleCycles
337 .name(thread_str + ".num_idle_cycles")
338 .desc("Number of idle cycles")
339 ;
269
340
270 statExecutedInstType
271 .init(Enums::Num_OpClass)
272 .name(name() + ".op_class")
273 .desc("Class of executed instruction")
274 .flags(total | pdf | dist)
275 ;
276 for (unsigned i = 0; i < Num_OpClasses; ++i) {
277 statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
278 }
341 t_info.icacheStallCycles
342 .name(thread_str + ".icache_stall_cycles")
343 .desc("ICache total stall cycles")
344 .prereq(t_info.icacheStallCycles)
345 ;
279
346
280 idleFraction = constant(1.0) - notIdleFraction;
281 numIdleCycles = idleFraction * numCycles;
282 numBusyCycles = (notIdleFraction)*numCycles;
347 t_info.dcacheStallCycles
348 .name(thread_str + ".dcache_stall_cycles")
349 .desc("DCache total stall cycles")
350 .prereq(t_info.dcacheStallCycles)
351 ;
283
352
284 numBranches
285 .name(name() + ".Branches")
286 .desc("Number of branches fetched")
287 .prereq(numBranches);
353 t_info.statExecutedInstType
354 .init(Enums::Num_OpClass)
355 .name(thread_str + ".op_class")
356 .desc("Class of executed instruction")
357 .flags(total | pdf | dist)
358 ;
288
359
289 numPredictedBranches
290 .name(name() + ".predictedBranches")
291 .desc("Number of branches predicted as taken")
292 .prereq(numPredictedBranches);
360 for (unsigned i = 0; i < Num_OpClasses; ++i) {
361 t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
362 }
293
363
294 numBranchMispred
295 .name(name() + ".BranchMispred")
296 .desc("Number of branch mispredictions")
297 .prereq(numBranchMispred);
364 t_info.idleFraction = constant(1.0) - t_info.notIdleFraction;
365 t_info.numIdleCycles = t_info.idleFraction * numCycles;
366 t_info.numBusyCycles = t_info.notIdleFraction * numCycles;
367
368 t_info.numBranches
369 .name(thread_str + ".Branches")
370 .desc("Number of branches fetched")
371 .prereq(t_info.numBranches);
372
373 t_info.numPredictedBranches
374 .name(thread_str + ".predictedBranches")
375 .desc("Number of branches predicted as taken")
376 .prereq(t_info.numPredictedBranches);
377
378 t_info.numBranchMispred
379 .name(thread_str + ".BranchMispred")
380 .desc("Number of branch mispredictions")
381 .prereq(t_info.numBranchMispred);
382 }
298}
299
300void
301BaseSimpleCPU::resetStats()
302{
383}
384
385void
386BaseSimpleCPU::resetStats()
387{
303// startNumInst = numInst;
304 notIdleFraction = (_status != Idle);
388 for (auto &thread_info : threadInfo) {
389 thread_info->notIdleFraction = (_status != Idle);
390 }
305}
306
307void
308BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
309{
310 assert(_status == Idle || _status == Running);
391}
392
393void
394BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
395{
396 assert(_status == Idle || _status == Running);
311 assert(tid == 0);
312
397
313 thread->serialize(cp);
398 threadInfo[tid]->thread->serialize(cp);
314}
315
316void
317BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid)
318{
399}
400
401void
402BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid)
403{
319 if (tid != 0)
320 fatal("Trying to load more than one thread into a SimpleCPU\n");
321 thread->unserialize(cp);
404 threadInfo[tid]->thread->unserialize(cp);
322}
323
324void
325change_thread_state(ThreadID tid, int activate, int priority)
326{
327}
328
329Addr
330BaseSimpleCPU::dbg_vtophys(Addr addr)
331{
405}
406
407void
408change_thread_state(ThreadID tid, int activate, int priority)
409{
410}
411
412Addr
413BaseSimpleCPU::dbg_vtophys(Addr addr)
414{
332 return vtophys(tc, addr);
415 return vtophys(threadContexts[curThread], addr);
333}
334
335void
336BaseSimpleCPU::wakeup()
337{
416}
417
418void
419BaseSimpleCPU::wakeup()
420{
338 getAddrMonitor()->gotWakeup = true;
421 getCpuAddrMonitor()->gotWakeup = true;
339
422
340 if (thread->status() != ThreadContext::Suspended)
341 return;
342
343 DPRINTF(Quiesce,"Suspended Processor awoke\n");
344 thread->activate();
423 for (ThreadID tid = 0; tid < numThreads; tid++) {
424 if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
425 DPRINTF(Quiesce,"Suspended Processor awoke\n");
426 threadInfo[tid]->thread->activate();
427 }
428 }
345}
346
347void
348BaseSimpleCPU::checkForInterrupts()
349{
429}
430
431void
432BaseSimpleCPU::checkForInterrupts()
433{
434 SimpleExecContext&t_info = *threadInfo[curThread];
435 SimpleThread* thread = t_info.thread;
436 ThreadContext* tc = thread->getTC();
437
350 if (checkInterrupts(tc)) {
351 Fault interrupt = interrupts->getInterrupt(tc);
352
353 if (interrupt != NoFault) {
438 if (checkInterrupts(tc)) {
439 Fault interrupt = interrupts->getInterrupt(tc);
440
441 if (interrupt != NoFault) {
354 fetchOffset = 0;
442 t_info.fetchOffset = 0;
355 interrupts->updateIntrInfo(tc);
356 interrupt->invoke(tc);
357 thread->decoder.reset();
358 }
359 }
360}
361
362
363void
364BaseSimpleCPU::setupFetchRequest(Request *req)
365{
443 interrupts->updateIntrInfo(tc);
444 interrupt->invoke(tc);
445 thread->decoder.reset();
446 }
447 }
448}
449
450
451void
452BaseSimpleCPU::setupFetchRequest(Request *req)
453{
454 SimpleExecContext &t_info = *threadInfo[curThread];
455 SimpleThread* thread = t_info.thread;
456
366 Addr instAddr = thread->instAddr();
367
368 // set up memory request for instruction fetch
369 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
370
457 Addr instAddr = thread->instAddr();
458
459 // set up memory request for instruction fetch
460 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
461
371 Addr fetchPC = (instAddr & PCMask) + fetchOffset;
462 Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
372 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
373 instAddr);
374}
375
376
377void
378BaseSimpleCPU::preExecute()
379{
463 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
464 instAddr);
465}
466
467
468void
469BaseSimpleCPU::preExecute()
470{
471 SimpleExecContext &t_info = *threadInfo[curThread];
472 SimpleThread* thread = t_info.thread;
473
380 // maintain $r0 semantics
381 thread->setIntReg(ZeroReg, 0);
382#if THE_ISA == ALPHA_ISA
383 thread->setFloatReg(ZeroReg, 0.0);
384#endif // ALPHA_ISA
385
386 // check for instruction-count-based events
474 // maintain $r0 semantics
475 thread->setIntReg(ZeroReg, 0);
476#if THE_ISA == ALPHA_ISA
477 thread->setFloatReg(ZeroReg, 0.0);
478#endif // ALPHA_ISA
479
480 // check for instruction-count-based events
387 comInstEventQueue[0]->serviceEvents(numInst);
481 comInstEventQueue[curThread]->serviceEvents(t_info.numInst);
388 system->instEventQueue.serviceEvents(system->totalNumInsts);
389
390 // decode the instruction
391 inst = gtoh(inst);
392
393 TheISA::PCState pcState = thread->pcState();
394
395 if (isRomMicroPC(pcState.microPC())) {
482 system->instEventQueue.serviceEvents(system->totalNumInsts);
483
484 // decode the instruction
485 inst = gtoh(inst);
486
487 TheISA::PCState pcState = thread->pcState();
488
489 if (isRomMicroPC(pcState.microPC())) {
396 stayAtPC = false;
490 t_info.stayAtPC = false;
397 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
398 curMacroStaticInst);
399 } else if (!curMacroStaticInst) {
400 //We're not in the middle of a macro instruction
401 StaticInstPtr instPtr = NULL;
402
403 TheISA::Decoder *decoder = &(thread->decoder);
404
405 //Predecode, ie bundle up an ExtMachInst
406 //If more fetch data is needed, pass it in.
491 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
492 curMacroStaticInst);
493 } else if (!curMacroStaticInst) {
494 //We're not in the middle of a macro instruction
495 StaticInstPtr instPtr = NULL;
496
497 TheISA::Decoder *decoder = &(thread->decoder);
498
499 //Predecode, ie bundle up an ExtMachInst
500 //If more fetch data is needed, pass it in.
407 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
501 Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset;
408 //if(decoder->needMoreBytes())
409 decoder->moreBytes(pcState, fetchPC, inst);
410 //else
411 // decoder->process();
412
413 //Decode an instruction if one is ready. Otherwise, we'll have to
414 //fetch beyond the MachInst at the current pc.
415 instPtr = decoder->decode(pcState);
416 if (instPtr) {
502 //if(decoder->needMoreBytes())
503 decoder->moreBytes(pcState, fetchPC, inst);
504 //else
505 // decoder->process();
506
507 //Decode an instruction if one is ready. Otherwise, we'll have to
508 //fetch beyond the MachInst at the current pc.
509 instPtr = decoder->decode(pcState);
510 if (instPtr) {
417 stayAtPC = false;
511 t_info.stayAtPC = false;
418 thread->pcState(pcState);
419 } else {
512 thread->pcState(pcState);
513 } else {
420 stayAtPC = true;
421 fetchOffset += sizeof(MachInst);
514 t_info.stayAtPC = true;
515 t_info.fetchOffset += sizeof(MachInst);
422 }
423
424 //If we decoded an instruction and it's microcoded, start pulling
425 //out micro ops
426 if (instPtr && instPtr->isMacroop()) {
427 curMacroStaticInst = instPtr;
516 }
517
518 //If we decoded an instruction and it's microcoded, start pulling
519 //out micro ops
520 if (instPtr && instPtr->isMacroop()) {
521 curMacroStaticInst = instPtr;
428 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
522 curStaticInst =
523 curMacroStaticInst->fetchMicroop(pcState.microPC());
429 } else {
430 curStaticInst = instPtr;
431 }
432 } else {
433 //Read the next micro op from the macro op
434 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
435 }
436
437 //If we decoded an instruction this "tick", record information about it.
438 if (curStaticInst) {
439#if TRACING_ON
524 } else {
525 curStaticInst = instPtr;
526 }
527 } else {
528 //Read the next micro op from the macro op
529 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
530 }
531
532 //If we decoded an instruction this "tick", record information about it.
533 if (curStaticInst) {
534#if TRACING_ON
440 traceData = tracer->getInstRecord(curTick(), tc,
535 traceData = tracer->getInstRecord(curTick(), thread->getTC(),
441 curStaticInst, thread->pcState(), curMacroStaticInst);
442
443 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
444 curStaticInst->getName(), curStaticInst->machInst);
445#endif // TRACING_ON
446 }
447
536 curStaticInst, thread->pcState(), curMacroStaticInst);
537
538 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
539 curStaticInst->getName(), curStaticInst->machInst);
540#endif // TRACING_ON
541 }
542
448 if (branchPred && curStaticInst && curStaticInst->isControl()) {
543 if (branchPred && curStaticInst &&
544 curStaticInst->isControl()) {
449 // Use a fake sequence number since we only have one
450 // instruction in flight at the same time.
451 const InstSeqNum cur_sn(0);
545 // Use a fake sequence number since we only have one
546 // instruction in flight at the same time.
547 const InstSeqNum cur_sn(0);
452 const ThreadID tid(0);
453 pred_pc = thread->pcState();
548 t_info.predPC = thread->pcState();
454 const bool predict_taken(
549 const bool predict_taken(
455 branchPred->predict(curStaticInst, cur_sn, pred_pc, tid));
550 branchPred->predict(curStaticInst, cur_sn, t_info.predPC,
551 curThread));
456
457 if (predict_taken)
552
553 if (predict_taken)
458 ++numPredictedBranches;
554 ++t_info.numPredictedBranches;
459 }
460}
461
462void
463BaseSimpleCPU::postExecute()
464{
555 }
556}
557
558void
559BaseSimpleCPU::postExecute()
560{
561 SimpleExecContext &t_info = *threadInfo[curThread];
562 SimpleThread* thread = t_info.thread;
563
465 assert(curStaticInst);
466
564 assert(curStaticInst);
565
467 TheISA::PCState pc = tc->pcState();
566 TheISA::PCState pc = threadContexts[curThread]->pcState();
468 Addr instAddr = pc.instAddr();
469 if (FullSystem && thread->profile) {
567 Addr instAddr = pc.instAddr();
568 if (FullSystem && thread->profile) {
470 bool usermode = TheISA::inUserMode(tc);
569 bool usermode = TheISA::inUserMode(threadContexts[curThread]);
471 thread->profilePC = usermode ? 1 : instAddr;
570 thread->profilePC = usermode ? 1 : instAddr;
472 ProfileNode *node = thread->profile->consume(tc, curStaticInst);
571 ProfileNode *node = thread->profile->consume(threadContexts[curThread],
572 curStaticInst);
473 if (node)
474 thread->profileNode = node;
475 }
476
477 if (curStaticInst->isMemRef()) {
573 if (node)
574 thread->profileNode = node;
575 }
576
577 if (curStaticInst->isMemRef()) {
478 numMemRefs++;
578 t_info.numMemRefs++;
479 }
480
481 if (curStaticInst->isLoad()) {
579 }
580
581 if (curStaticInst->isLoad()) {
482 ++numLoad;
483 comLoadEventQueue[0]->serviceEvents(numLoad);
582 ++t_info.numLoad;
583 comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad);
484 }
485
486 if (CPA::available()) {
584 }
585
586 if (CPA::available()) {
487 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
587 CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr());
488 }
489
490 if (curStaticInst->isControl()) {
588 }
589
590 if (curStaticInst->isControl()) {
491 ++numBranches;
591 ++t_info.numBranches;
492 }
493
494 /* Power model statistics */
495 //integer alu accesses
496 if (curStaticInst->isInteger()){
592 }
593
594 /* Power model statistics */
595 //integer alu accesses
596 if (curStaticInst->isInteger()){
497 numIntAluAccesses++;
498 numIntInsts++;
597 t_info.numIntAluAccesses++;
598 t_info.numIntInsts++;
499 }
500
501 //float alu accesses
502 if (curStaticInst->isFloating()){
599 }
600
601 //float alu accesses
602 if (curStaticInst->isFloating()){
503 numFpAluAccesses++;
504 numFpInsts++;
603 t_info.numFpAluAccesses++;
604 t_info.numFpInsts++;
505 }
605 }
506
606
507 //number of function calls/returns to get window accesses
508 if (curStaticInst->isCall() || curStaticInst->isReturn()){
607 //number of function calls/returns to get window accesses
608 if (curStaticInst->isCall() || curStaticInst->isReturn()){
509 numCallsReturns++;
609 t_info.numCallsReturns++;
510 }
610 }
511
611
512 //the number of branch predictions that will be made
513 if (curStaticInst->isCondCtrl()){
612 //the number of branch predictions that will be made
613 if (curStaticInst->isCondCtrl()){
514 numCondCtrlInsts++;
614 t_info.numCondCtrlInsts++;
515 }
615 }
516
616
517 //result bus acceses
518 if (curStaticInst->isLoad()){
617 //result bus acceses
618 if (curStaticInst->isLoad()){
519 numLoadInsts++;
619 t_info.numLoadInsts++;
520 }
620 }
521
621
522 if (curStaticInst->isStore()){
622 if (curStaticInst->isStore()){
523 numStoreInsts++;
623 t_info.numStoreInsts++;
524 }
525 /* End power model statistics */
526
624 }
625 /* End power model statistics */
626
527 statExecutedInstType[curStaticInst->opClass()]++;
627 t_info.statExecutedInstType[curStaticInst->opClass()]++;
528
529 if (FullSystem)
530 traceFunctions(instAddr);
531
532 if (traceData) {
533 traceData->dump();
534 delete traceData;
535 traceData = NULL;
536 }
537
538 // Call CPU instruction commit probes
539 probeInstCommit(curStaticInst);
540}
541
542void
543BaseSimpleCPU::advancePC(const Fault &fault)
544{
628
629 if (FullSystem)
630 traceFunctions(instAddr);
631
632 if (traceData) {
633 traceData->dump();
634 delete traceData;
635 traceData = NULL;
636 }
637
638 // Call CPU instruction commit probes
639 probeInstCommit(curStaticInst);
640}
641
642void
643BaseSimpleCPU::advancePC(const Fault &fault)
644{
645 SimpleExecContext &t_info = *threadInfo[curThread];
646 SimpleThread* thread = t_info.thread;
647
545 const bool branching(thread->pcState().branching());
546
547 //Since we're moving to a new pc, zero out the offset
648 const bool branching(thread->pcState().branching());
649
650 //Since we're moving to a new pc, zero out the offset
548 fetchOffset = 0;
651 t_info.fetchOffset = 0;
549 if (fault != NoFault) {
550 curMacroStaticInst = StaticInst::nullStaticInstPtr;
652 if (fault != NoFault) {
653 curMacroStaticInst = StaticInst::nullStaticInstPtr;
551 fault->invoke(tc, curStaticInst);
654 fault->invoke(threadContexts[curThread], curStaticInst);
552 thread->decoder.reset();
553 } else {
554 if (curStaticInst) {
555 if (curStaticInst->isLastMicroop())
556 curMacroStaticInst = StaticInst::nullStaticInstPtr;
557 TheISA::PCState pcState = thread->pcState();
558 TheISA::advancePC(pcState, curStaticInst);
559 thread->pcState(pcState);
560 }
561 }
562
563 if (branchPred && curStaticInst && curStaticInst->isControl()) {
564 // Use a fake sequence number since we only have one
565 // instruction in flight at the same time.
566 const InstSeqNum cur_sn(0);
655 thread->decoder.reset();
656 } else {
657 if (curStaticInst) {
658 if (curStaticInst->isLastMicroop())
659 curMacroStaticInst = StaticInst::nullStaticInstPtr;
660 TheISA::PCState pcState = thread->pcState();
661 TheISA::advancePC(pcState, curStaticInst);
662 thread->pcState(pcState);
663 }
664 }
665
666 if (branchPred && curStaticInst && curStaticInst->isControl()) {
667 // Use a fake sequence number since we only have one
668 // instruction in flight at the same time.
669 const InstSeqNum cur_sn(0);
567 const ThreadID tid(0);
568
670
569 if (pred_pc == thread->pcState()) {
671 if (t_info.predPC == thread->pcState()) {
570 // Correctly predicted branch
672 // Correctly predicted branch
571 branchPred->update(cur_sn, tid);
673 branchPred->update(cur_sn, curThread);
572 } else {
573 // Mis-predicted branch
674 } else {
675 // Mis-predicted branch
574 branchPred->squash(cur_sn, pcState(),
575 branching, tid);
576 ++numBranchMispred;
676 branchPred->squash(cur_sn, thread->pcState(), branching, curThread);
677 ++t_info.numBranchMispred;
577 }
578 }
579}
580
581void
582BaseSimpleCPU::startup()
583{
584 BaseCPU::startup();
678 }
679 }
680}
681
682void
683BaseSimpleCPU::startup()
684{
685 BaseCPU::startup();
585 thread->startup();
686 for (auto& t_info : threadInfo)
687 t_info->thread->startup();
586}
688}