base.cc (10529:05b5a6cf3521) base.cc (10537:47fe87b0cf97)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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83#include "sim/system.hh"
84
85using namespace std;
86using namespace TheISA;
87
88BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
89 : BaseCPU(p),
90 branchPred(p->branchPred),
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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83#include "sim/system.hh"
84
85using namespace std;
86using namespace TheISA;
87
88BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
89 : BaseCPU(p),
90 branchPred(p->branchPred),
91 traceData(NULL), thread(NULL)
91 traceData(NULL), thread(NULL), _status(Idle), interval_stats(false),
92 inst()
92{
93 if (FullSystem)
94 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
95 p->isa[0]);
96 else
97 thread = new SimpleThread(this, /* thread_num */ 0, p->system,
98 p->workload[0], p->itb, p->dtb, p->isa[0]);
99

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261 ;
262
263 dcacheStallCycles
264 .name(name() + ".dcache_stall_cycles")
265 .desc("DCache total stall cycles")
266 .prereq(dcacheStallCycles)
267 ;
268
93{
94 if (FullSystem)
95 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
96 p->isa[0]);
97 else
98 thread = new SimpleThread(this, /* thread_num */ 0, p->system,
99 p->workload[0], p->itb, p->dtb, p->isa[0]);
100

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262 ;
263
264 dcacheStallCycles
265 .name(name() + ".dcache_stall_cycles")
266 .desc("DCache total stall cycles")
267 .prereq(dcacheStallCycles)
268 ;
269
269 icacheRetryCycles
270 .name(name() + ".icache_retry_cycles")
271 .desc("ICache total retry cycles")
272 .prereq(icacheRetryCycles)
273 ;
274
275 dcacheRetryCycles
276 .name(name() + ".dcache_retry_cycles")
277 .desc("DCache total retry cycles")
278 .prereq(dcacheRetryCycles)
279 ;
280
281 statExecutedInstType
282 .init(Enums::Num_OpClass)
283 .name(name() + ".op_class")
284 .desc("Class of executed instruction")
285 .flags(total | pdf | dist)
286 ;
287 for (unsigned i = 0; i < Num_OpClasses; ++i) {
288 statExecutedInstType.subname(i, Enums::OpClassStrings[i]);

--- 310 unchanged lines hidden --- 		270 statExecutedInstType
271 .init(Enums::Num_OpClass)
272 .name(name() + ".op_class")
273 .desc("Class of executed instruction")
274 .flags(total | pdf | dist)
275 ;
276 for (unsigned i = 0; i < Num_OpClasses; ++i) {
277 statExecutedInstType.subname(i, Enums::OpClassStrings[i]);

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