1/*
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2 * Copyright (c) 2010-2012 ARM Limited
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2 * Copyright (c) 2010-2012,2015 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "arch/kernel_stats.hh" 45#include "arch/stacktrace.hh" 46#include "arch/tlb.hh" 47#include "arch/utility.hh" 48#include "arch/vtophys.hh" 49#include "base/loader/symtab.hh" 50#include "base/cp_annotate.hh" 51#include "base/cprintf.hh" 52#include "base/inifile.hh" 53#include "base/misc.hh" 54#include "base/pollevent.hh" 55#include "base/trace.hh" 56#include "base/types.hh" 57#include "config/the_isa.hh" 58#include "cpu/simple/base.hh" 59#include "cpu/base.hh" 60#include "cpu/checker/cpu.hh" 61#include "cpu/checker/thread_context.hh" 62#include "cpu/exetrace.hh" 63#include "cpu/pred/bpred_unit.hh" 64#include "cpu/profile.hh"
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65#include "cpu/simple/exec_context.hh" |
66#include "cpu/simple_thread.hh" 67#include "cpu/smt.hh" 68#include "cpu/static_inst.hh" 69#include "cpu/thread_context.hh" 70#include "debug/Decode.hh" 71#include "debug/Fetch.hh" 72#include "debug/Quiesce.hh" 73#include "mem/mem_object.hh" 74#include "mem/packet.hh" 75#include "mem/request.hh" 76#include "params/BaseSimpleCPU.hh" 77#include "sim/byteswap.hh" 78#include "sim/debug.hh" 79#include "sim/faults.hh" 80#include "sim/full_system.hh" 81#include "sim/sim_events.hh" 82#include "sim/sim_object.hh" 83#include "sim/stats.hh" 84#include "sim/system.hh" 85 86using namespace std; 87using namespace TheISA; 88 89BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 90 : BaseCPU(p),
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91 curThread(0), |
92 branchPred(p->branchPred),
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91 traceData(NULL), thread(NULL), _status(Idle), interval_stats(false),
92 inst()
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93 traceData(NULL), 94 inst(), 95 _status(Idle) |
96{
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94 if (FullSystem)
95 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
96 p->isa[0]);
97 else
98 thread = new SimpleThread(this, /* thread_num */ 0, p->system,
99 p->workload[0], p->itb, p->dtb, p->isa[0]);
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97 SimpleThread *thread; |
98
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101 thread->setStatus(ThreadContext::Halted);
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99 for (unsigned i = 0; i < numThreads; i++) { 100 if (FullSystem) { 101 thread = new SimpleThread(this, i, p->system, 102 p->itb, p->dtb, p->isa[i]); 103 } else { 104 thread = new SimpleThread(this, i, p->system, p->workload[i], 105 p->itb, p->dtb, p->isa[i]); 106 } 107 threadInfo.push_back(new SimpleExecContext(this, thread)); 108 ThreadContext *tc = thread->getTC(); 109 threadContexts.push_back(tc); 110 } |
111
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103 tc = thread->getTC();
104
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112 if (p->checker) {
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113 if (numThreads != 1) 114 fatal("Checker currently does not support SMT"); 115 |
116 BaseCPU *temp_checker = p->checker; 117 checker = dynamic_cast<CheckerCPU *>(temp_checker); 118 checker->setSystem(p->system); 119 // Manipulate thread context
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110 ThreadContext *cpu_tc = tc;
111 tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
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120 ThreadContext *cpu_tc = threadContexts[0]; 121 threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); |
122 } else { 123 checker = NULL; 124 }
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125} |
126
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116 numInst = 0;
117 startNumInst = 0;
118 numOp = 0;
119 startNumOp = 0;
120 numLoad = 0;
121 startNumLoad = 0;
122 lastIcacheStall = 0;
123 lastDcacheStall = 0;
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127void 128BaseSimpleCPU::init() 129{ 130 BaseCPU::init(); |
131
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125 threadContexts.push_back(tc);
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132 for (auto tc : threadContexts) { 133 // Initialise the ThreadContext's memory proxies 134 tc->initMemProxies(tc); |
135
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136 if (FullSystem && !params()->switched_out) { 137 // initialize CPU, including PC 138 TheISA::initCPU(tc, tc->contextId()); 139 } 140 } 141} |
142
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128 fetchOffset = 0;
129 stayAtPC = false;
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143void 144BaseSimpleCPU::checkPcEventQueue() 145{ 146 Addr oldpc, pc = threadInfo[curThread]->thread->instAddr(); 147 do { 148 oldpc = pc; 149 system->pcEventQueue.service(threadContexts[curThread]); 150 pc = threadInfo[curThread]->thread->instAddr(); 151 } while (oldpc != pc); |
152} 153
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154void 155BaseSimpleCPU::swapActiveThread() 156{ 157 if (numThreads > 1) { 158 if ((!curStaticInst || !curStaticInst->isDelayedCommit()) && 159 !threadInfo[curThread]->stayAtPC) { 160 // Swap active threads 161 if (!activeThreads.empty()) { 162 curThread = activeThreads.front(); 163 activeThreads.pop_front(); 164 activeThreads.push_back(curThread); 165 } 166 } 167 } 168} 169 170void 171BaseSimpleCPU::countInst() 172{ 173 SimpleExecContext& t_info = *threadInfo[curThread]; 174 175 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { 176 t_info.numInst++; 177 t_info.numInsts++; 178 } 179 t_info.numOp++; 180 t_info.numOps++; 181 182 system->totalNumInsts++; 183 t_info.thread->funcExeInst++; 184} 185 186Counter 187BaseSimpleCPU::totalInsts() const 188{ 189 Counter total_inst = 0; 190 for (auto& t_info : threadInfo) { 191 total_inst += t_info->numInst; 192 } 193 194 return total_inst; 195} 196 197Counter 198BaseSimpleCPU::totalOps() const 199{ 200 Counter total_op = 0; 201 for (auto& t_info : threadInfo) { 202 total_op += t_info->numOp; 203 } 204 205 return total_op; 206} 207 |
208BaseSimpleCPU::~BaseSimpleCPU() 209{ 210} 211 212void 213BaseSimpleCPU::haltContext(ThreadID thread_num) 214{ 215 // for now, these are equivalent 216 suspendContext(thread_num); 217} 218 219 220void 221BaseSimpleCPU::regStats() 222{ 223 using namespace Stats; 224 225 BaseCPU::regStats(); 226
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151 numInsts
152 .name(name() + ".committedInsts")
153 .desc("Number of instructions committed")
154 ;
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227 for (ThreadID tid = 0; tid < numThreads; tid++) { 228 SimpleExecContext& t_info = *threadInfo[tid]; |
229
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156 numOps
157 .name(name() + ".committedOps")
158 .desc("Number of ops (including micro ops) committed")
159 ;
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230 std::string thread_str = name(); 231 if (numThreads > 1) 232 thread_str += ".thread" + std::to_string(tid); |
233
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161 numIntAluAccesses
162 .name(name() + ".num_int_alu_accesses")
163 .desc("Number of integer alu accesses")
164 ;
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234 t_info.numInsts 235 .name(thread_str + ".committedInsts") 236 .desc("Number of instructions committed") 237 ; |
238
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166 numFpAluAccesses
167 .name(name() + ".num_fp_alu_accesses")
168 .desc("Number of float alu accesses")
169 ;
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239 t_info.numOps 240 .name(thread_str + ".committedOps") 241 .desc("Number of ops (including micro ops) committed") 242 ; |
243
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171 numCallsReturns
172 .name(name() + ".num_func_calls")
173 .desc("number of times a function call or return occured")
174 ;
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244 t_info.numIntAluAccesses 245 .name(thread_str + ".num_int_alu_accesses") 246 .desc("Number of integer alu accesses") 247 ; |
248
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176 numCondCtrlInsts
177 .name(name() + ".num_conditional_control_insts")
178 .desc("number of instructions that are conditional controls")
179 ;
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249 t_info.numFpAluAccesses 250 .name(thread_str + ".num_fp_alu_accesses") 251 .desc("Number of float alu accesses") 252 ; |
253
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181 numIntInsts
182 .name(name() + ".num_int_insts")
183 .desc("number of integer instructions")
184 ;
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254 t_info.numCallsReturns 255 .name(thread_str + ".num_func_calls") 256 .desc("number of times a function call or return occured") 257 ; |
258
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186 numFpInsts
187 .name(name() + ".num_fp_insts")
188 .desc("number of float instructions")
189 ;
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259 t_info.numCondCtrlInsts 260 .name(thread_str + ".num_conditional_control_insts") 261 .desc("number of instructions that are conditional controls") 262 ; |
263
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191 numIntRegReads
192 .name(name() + ".num_int_register_reads")
193 .desc("number of times the integer registers were read")
194 ;
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264 t_info.numIntInsts 265 .name(thread_str + ".num_int_insts") 266 .desc("number of integer instructions") 267 ; |
268
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196 numIntRegWrites
197 .name(name() + ".num_int_register_writes")
198 .desc("number of times the integer registers were written")
199 ;
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269 t_info.numFpInsts 270 .name(thread_str + ".num_fp_insts") 271 .desc("number of float instructions") 272 ; |
273
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201 numFpRegReads
202 .name(name() + ".num_fp_register_reads")
203 .desc("number of times the floating registers were read")
204 ;
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274 t_info.numIntRegReads 275 .name(thread_str + ".num_int_register_reads") 276 .desc("number of times the integer registers were read") 277 ; |
278
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206 numFpRegWrites
207 .name(name() + ".num_fp_register_writes")
208 .desc("number of times the floating registers were written")
209 ;
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279 t_info.numIntRegWrites 280 .name(thread_str + ".num_int_register_writes") 281 .desc("number of times the integer registers were written") 282 ; |
283
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211 numCCRegReads
212 .name(name() + ".num_cc_register_reads")
213 .desc("number of times the CC registers were read")
214 .flags(nozero)
215 ;
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284 t_info.numFpRegReads 285 .name(thread_str + ".num_fp_register_reads") 286 .desc("number of times the floating registers were read") 287 ; |
288
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217 numCCRegWrites
218 .name(name() + ".num_cc_register_writes")
219 .desc("number of times the CC registers were written")
220 .flags(nozero)
221 ;
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289 t_info.numFpRegWrites 290 .name(thread_str + ".num_fp_register_writes") 291 .desc("number of times the floating registers were written") 292 ; |
293
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223 numMemRefs
224 .name(name()+".num_mem_refs")
225 .desc("number of memory refs")
226 ;
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294 t_info.numCCRegReads 295 .name(thread_str + ".num_cc_register_reads") 296 .desc("number of times the CC registers were read") 297 .flags(nozero) 298 ; |
299
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228 numStoreInsts
229 .name(name() + ".num_store_insts")
230 .desc("Number of store instructions")
231 ;
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300 t_info.numCCRegWrites 301 .name(thread_str + ".num_cc_register_writes") 302 .desc("number of times the CC registers were written") 303 .flags(nozero) 304 ; |
305
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233 numLoadInsts
234 .name(name() + ".num_load_insts")
235 .desc("Number of load instructions")
236 ;
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306 t_info.numMemRefs 307 .name(thread_str + ".num_mem_refs") 308 .desc("number of memory refs") 309 ; |
310
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238 notIdleFraction
239 .name(name() + ".not_idle_fraction")
240 .desc("Percentage of non-idle cycles")
241 ;
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311 t_info.numStoreInsts 312 .name(thread_str + ".num_store_insts") 313 .desc("Number of store instructions") 314 ; |
315
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243 idleFraction
244 .name(name() + ".idle_fraction")
245 .desc("Percentage of idle cycles")
246 ;
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316 t_info.numLoadInsts 317 .name(thread_str + ".num_load_insts") 318 .desc("Number of load instructions") 319 ; |
320
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248 numBusyCycles
249 .name(name() + ".num_busy_cycles")
250 .desc("Number of busy cycles")
251 ;
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321 t_info.notIdleFraction 322 .name(thread_str + ".not_idle_fraction") 323 .desc("Percentage of non-idle cycles") 324 ; |
325
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253 numIdleCycles
254 .name(name()+".num_idle_cycles")
255 .desc("Number of idle cycles")
256 ;
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326 t_info.idleFraction 327 .name(thread_str + ".idle_fraction") 328 .desc("Percentage of idle cycles") 329 ; |
330
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258 icacheStallCycles
259 .name(name() + ".icache_stall_cycles")
260 .desc("ICache total stall cycles")
261 .prereq(icacheStallCycles)
262 ;
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331 t_info.numBusyCycles 332 .name(thread_str + ".num_busy_cycles") 333 .desc("Number of busy cycles") 334 ; |
335
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264 dcacheStallCycles
265 .name(name() + ".dcache_stall_cycles")
266 .desc("DCache total stall cycles")
267 .prereq(dcacheStallCycles)
268 ;
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336 t_info.numIdleCycles 337 .name(thread_str + ".num_idle_cycles") 338 .desc("Number of idle cycles") 339 ; |
340
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270 statExecutedInstType
271 .init(Enums::Num_OpClass)
272 .name(name() + ".op_class")
273 .desc("Class of executed instruction")
274 .flags(total | pdf | dist)
275 ;
276 for (unsigned i = 0; i < Num_OpClasses; ++i) {
277 statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
278 }
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341 t_info.icacheStallCycles 342 .name(thread_str + ".icache_stall_cycles") 343 .desc("ICache total stall cycles") 344 .prereq(t_info.icacheStallCycles) 345 ; |
346
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280 idleFraction = constant(1.0) - notIdleFraction;
281 numIdleCycles = idleFraction * numCycles;
282 numBusyCycles = (notIdleFraction)*numCycles;
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347 t_info.dcacheStallCycles 348 .name(thread_str + ".dcache_stall_cycles") 349 .desc("DCache total stall cycles") 350 .prereq(t_info.dcacheStallCycles) 351 ; |
352
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284 numBranches
285 .name(name() + ".Branches")
286 .desc("Number of branches fetched")
287 .prereq(numBranches);
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353 t_info.statExecutedInstType 354 .init(Enums::Num_OpClass) 355 .name(thread_str + ".op_class") 356 .desc("Class of executed instruction") 357 .flags(total | pdf | dist) 358 ; |
359
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289 numPredictedBranches
290 .name(name() + ".predictedBranches")
291 .desc("Number of branches predicted as taken")
292 .prereq(numPredictedBranches);
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360 for (unsigned i = 0; i < Num_OpClasses; ++i) { 361 t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]); 362 } |
363
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294 numBranchMispred
295 .name(name() + ".BranchMispred")
296 .desc("Number of branch mispredictions")
297 .prereq(numBranchMispred);
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364 t_info.idleFraction = constant(1.0) - t_info.notIdleFraction; 365 t_info.numIdleCycles = t_info.idleFraction * numCycles; 366 t_info.numBusyCycles = t_info.notIdleFraction * numCycles; 367 368 t_info.numBranches 369 .name(thread_str + ".Branches") 370 .desc("Number of branches fetched") 371 .prereq(t_info.numBranches); 372 373 t_info.numPredictedBranches 374 .name(thread_str + ".predictedBranches") 375 .desc("Number of branches predicted as taken") 376 .prereq(t_info.numPredictedBranches); 377 378 t_info.numBranchMispred 379 .name(thread_str + ".BranchMispred") 380 .desc("Number of branch mispredictions") 381 .prereq(t_info.numBranchMispred); 382 } |
383} 384 385void 386BaseSimpleCPU::resetStats() 387{
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303// startNumInst = numInst;
304 notIdleFraction = (_status != Idle);
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388 for (auto &thread_info : threadInfo) { 389 thread_info->notIdleFraction = (_status != Idle); 390 } |
391} 392 393void 394BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const 395{ 396 assert(_status == Idle || _status == Running);
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311 assert(tid == 0);
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397
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313 thread->serialize(cp);
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398 threadInfo[tid]->thread->serialize(cp); |
399} 400 401void 402BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid) 403{
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319 if (tid != 0)
320 fatal("Trying to load more than one thread into a SimpleCPU\n");
321 thread->unserialize(cp);
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404 threadInfo[tid]->thread->unserialize(cp); |
405} 406 407void 408change_thread_state(ThreadID tid, int activate, int priority) 409{ 410} 411 412Addr 413BaseSimpleCPU::dbg_vtophys(Addr addr) 414{
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332 return vtophys(tc, addr);
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415 return vtophys(threadContexts[curThread], addr); |
416} 417 418void 419BaseSimpleCPU::wakeup() 420{
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338 getAddrMonitor()->gotWakeup = true;
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421 getCpuAddrMonitor()->gotWakeup = true; |
422
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340 if (thread->status() != ThreadContext::Suspended)
341 return;
342
343 DPRINTF(Quiesce,"Suspended Processor awoke\n");
344 thread->activate();
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423 for (ThreadID tid = 0; tid < numThreads; tid++) { 424 if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) { 425 DPRINTF(Quiesce,"Suspended Processor awoke\n"); 426 threadInfo[tid]->thread->activate(); 427 } 428 } |
429} 430 431void 432BaseSimpleCPU::checkForInterrupts() 433{
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434 SimpleExecContext&t_info = *threadInfo[curThread]; 435 SimpleThread* thread = t_info.thread; 436 ThreadContext* tc = thread->getTC(); 437 |
438 if (checkInterrupts(tc)) { 439 Fault interrupt = interrupts->getInterrupt(tc); 440 441 if (interrupt != NoFault) {
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354 fetchOffset = 0;
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442 t_info.fetchOffset = 0; |
443 interrupts->updateIntrInfo(tc); 444 interrupt->invoke(tc); 445 thread->decoder.reset(); 446 } 447 } 448} 449 450 451void 452BaseSimpleCPU::setupFetchRequest(Request *req) 453{
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454 SimpleExecContext &t_info = *threadInfo[curThread]; 455 SimpleThread* thread = t_info.thread; 456 |
457 Addr instAddr = thread->instAddr(); 458 459 // set up memory request for instruction fetch 460 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 461
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371 Addr fetchPC = (instAddr & PCMask) + fetchOffset;
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462 Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset; |
463 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 464 instAddr); 465} 466 467 468void 469BaseSimpleCPU::preExecute() 470{
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471 SimpleExecContext &t_info = *threadInfo[curThread]; 472 SimpleThread* thread = t_info.thread; 473 |
474 // maintain $r0 semantics 475 thread->setIntReg(ZeroReg, 0); 476#if THE_ISA == ALPHA_ISA 477 thread->setFloatReg(ZeroReg, 0.0); 478#endif // ALPHA_ISA 479 480 // check for instruction-count-based events
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387 comInstEventQueue[0]->serviceEvents(numInst);
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481 comInstEventQueue[curThread]->serviceEvents(t_info.numInst); |
482 system->instEventQueue.serviceEvents(system->totalNumInsts); 483 484 // decode the instruction 485 inst = gtoh(inst); 486 487 TheISA::PCState pcState = thread->pcState(); 488 489 if (isRomMicroPC(pcState.microPC())) {
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396 stayAtPC = false;
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490 t_info.stayAtPC = false; |
491 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 492 curMacroStaticInst); 493 } else if (!curMacroStaticInst) { 494 //We're not in the middle of a macro instruction 495 StaticInstPtr instPtr = NULL; 496 497 TheISA::Decoder *decoder = &(thread->decoder); 498 499 //Predecode, ie bundle up an ExtMachInst 500 //If more fetch data is needed, pass it in.
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407 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
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501 Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset; |
502 //if(decoder->needMoreBytes()) 503 decoder->moreBytes(pcState, fetchPC, inst); 504 //else 505 // decoder->process(); 506 507 //Decode an instruction if one is ready. Otherwise, we'll have to 508 //fetch beyond the MachInst at the current pc. 509 instPtr = decoder->decode(pcState); 510 if (instPtr) {
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417 stayAtPC = false;
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511 t_info.stayAtPC = false; |
512 thread->pcState(pcState); 513 } else {
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420 stayAtPC = true;
421 fetchOffset += sizeof(MachInst);
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514 t_info.stayAtPC = true; 515 t_info.fetchOffset += sizeof(MachInst); |
516 } 517 518 //If we decoded an instruction and it's microcoded, start pulling 519 //out micro ops 520 if (instPtr && instPtr->isMacroop()) { 521 curMacroStaticInst = instPtr;
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428 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
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522 curStaticInst = 523 curMacroStaticInst->fetchMicroop(pcState.microPC()); |
524 } else { 525 curStaticInst = instPtr; 526 } 527 } else { 528 //Read the next micro op from the macro op 529 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 530 } 531 532 //If we decoded an instruction this "tick", record information about it. 533 if (curStaticInst) { 534#if TRACING_ON
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440 traceData = tracer->getInstRecord(curTick(), tc,
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535 traceData = tracer->getInstRecord(curTick(), thread->getTC(), |
536 curStaticInst, thread->pcState(), curMacroStaticInst); 537 538 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 539 curStaticInst->getName(), curStaticInst->machInst); 540#endif // TRACING_ON 541 } 542
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448 if (branchPred && curStaticInst && curStaticInst->isControl()) {
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543 if (branchPred && curStaticInst && 544 curStaticInst->isControl()) { |
545 // Use a fake sequence number since we only have one 546 // instruction in flight at the same time. 547 const InstSeqNum cur_sn(0);
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452 const ThreadID tid(0);
453 pred_pc = thread->pcState();
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548 t_info.predPC = thread->pcState(); |
549 const bool predict_taken(
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455 branchPred->predict(curStaticInst, cur_sn, pred_pc, tid));
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550 branchPred->predict(curStaticInst, cur_sn, t_info.predPC, 551 curThread)); |
552 553 if (predict_taken)
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458 ++numPredictedBranches;
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554 ++t_info.numPredictedBranches; |
555 } 556} 557 558void 559BaseSimpleCPU::postExecute() 560{
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561 SimpleExecContext &t_info = *threadInfo[curThread]; 562 SimpleThread* thread = t_info.thread; 563 |
564 assert(curStaticInst); 565
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467 TheISA::PCState pc = tc->pcState();
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566 TheISA::PCState pc = threadContexts[curThread]->pcState(); |
567 Addr instAddr = pc.instAddr(); 568 if (FullSystem && thread->profile) {
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470 bool usermode = TheISA::inUserMode(tc);
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569 bool usermode = TheISA::inUserMode(threadContexts[curThread]); |
570 thread->profilePC = usermode ? 1 : instAddr;
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472 ProfileNode *node = thread->profile->consume(tc, curStaticInst);
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571 ProfileNode *node = thread->profile->consume(threadContexts[curThread], 572 curStaticInst); |
573 if (node) 574 thread->profileNode = node; 575 } 576 577 if (curStaticInst->isMemRef()) {
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478 numMemRefs++;
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578 t_info.numMemRefs++; |
579 } 580 581 if (curStaticInst->isLoad()) {
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482 ++numLoad;
483 comLoadEventQueue[0]->serviceEvents(numLoad);
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582 ++t_info.numLoad; 583 comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad); |
584 } 585 586 if (CPA::available()) {
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487 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
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587 CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr()); |
588 } 589 590 if (curStaticInst->isControl()) {
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491 ++numBranches;
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591 ++t_info.numBranches; |
592 } 593 594 /* Power model statistics */ 595 //integer alu accesses 596 if (curStaticInst->isInteger()){
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497 numIntAluAccesses++;
498 numIntInsts++;
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597 t_info.numIntAluAccesses++; 598 t_info.numIntInsts++; |
599 } 600 601 //float alu accesses 602 if (curStaticInst->isFloating()){
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503 numFpAluAccesses++;
504 numFpInsts++;
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603 t_info.numFpAluAccesses++; 604 t_info.numFpInsts++; |
605 }
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506
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606 |
607 //number of function calls/returns to get window accesses 608 if (curStaticInst->isCall() || curStaticInst->isReturn()){
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509 numCallsReturns++;
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609 t_info.numCallsReturns++; |
610 }
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511
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611 |
612 //the number of branch predictions that will be made 613 if (curStaticInst->isCondCtrl()){
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514 numCondCtrlInsts++;
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614 t_info.numCondCtrlInsts++; |
615 }
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516
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616 |
617 //result bus acceses 618 if (curStaticInst->isLoad()){
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519 numLoadInsts++;
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619 t_info.numLoadInsts++; |
620 }
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521
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621 |
622 if (curStaticInst->isStore()){
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523 numStoreInsts++;
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623 t_info.numStoreInsts++; |
624 } 625 /* End power model statistics */ 626
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527 statExecutedInstType[curStaticInst->opClass()]++;
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627 t_info.statExecutedInstType[curStaticInst->opClass()]++; |
628 629 if (FullSystem) 630 traceFunctions(instAddr); 631 632 if (traceData) { 633 traceData->dump(); 634 delete traceData; 635 traceData = NULL; 636 } 637 638 // Call CPU instruction commit probes 639 probeInstCommit(curStaticInst); 640} 641 642void 643BaseSimpleCPU::advancePC(const Fault &fault) 644{
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645 SimpleExecContext &t_info = *threadInfo[curThread]; 646 SimpleThread* thread = t_info.thread; 647 |
648 const bool branching(thread->pcState().branching()); 649 650 //Since we're moving to a new pc, zero out the offset
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548 fetchOffset = 0;
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651 t_info.fetchOffset = 0; |
652 if (fault != NoFault) { 653 curMacroStaticInst = StaticInst::nullStaticInstPtr;
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551 fault->invoke(tc, curStaticInst);
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654 fault->invoke(threadContexts[curThread], curStaticInst); |
655 thread->decoder.reset(); 656 } else { 657 if (curStaticInst) { 658 if (curStaticInst->isLastMicroop()) 659 curMacroStaticInst = StaticInst::nullStaticInstPtr; 660 TheISA::PCState pcState = thread->pcState(); 661 TheISA::advancePC(pcState, curStaticInst); 662 thread->pcState(pcState); 663 } 664 } 665 666 if (branchPred && curStaticInst && curStaticInst->isControl()) { 667 // Use a fake sequence number since we only have one 668 // instruction in flight at the same time. 669 const InstSeqNum cur_sn(0);
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567 const ThreadID tid(0);
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670
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569 if (pred_pc == thread->pcState()) {
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671 if (t_info.predPC == thread->pcState()) { |
672 // Correctly predicted branch
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571 branchPred->update(cur_sn, tid);
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673 branchPred->update(cur_sn, curThread); |
674 } else { 675 // Mis-predicted branch
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574 branchPred->squash(cur_sn, pcState(),
575 branching, tid);
576 ++numBranchMispred;
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676 branchPred->squash(cur_sn, thread->pcState(), branching, curThread); 677 ++t_info.numBranchMispred; |
678 } 679 } 680} 681 682void 683BaseSimpleCPU::startup() 684{ 685 BaseCPU::startup();
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585 thread->startup();
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686 for (auto& t_info : threadInfo) 687 t_info->thread->startup(); |
688}
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