1/* |
2 * Copyright (c) 2010 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 25 unchanged lines hidden (view full) --- 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#include "arch/faults.hh" |
44#include "arch/kernel_stats.hh" 45#include "arch/stacktrace.hh" 46#include "arch/tlb.hh" |
47#include "arch/utility.hh" |
48#include "arch/vtophys.hh" |
49#include "base/loader/symtab.hh" 50#include "base/cp_annotate.hh" 51#include "base/cprintf.hh" 52#include "base/inifile.hh" 53#include "base/misc.hh" 54#include "base/pollevent.hh" 55#include "base/range.hh" 56#include "base/trace.hh" 57#include "base/types.hh" 58#include "config/the_isa.hh" |
59#include "cpu/simple/base.hh" 60#include "cpu/base.hh" 61#include "cpu/exetrace.hh" 62#include "cpu/profile.hh" 63#include "cpu/simple_thread.hh" 64#include "cpu/smt.hh" 65#include "cpu/static_inst.hh" 66#include "cpu/thread_context.hh" 67#include "debug/Decode.hh" 68#include "debug/Fetch.hh" 69#include "debug/Quiesce.hh" |
70#include "mem/mem_object.hh" |
71#include "mem/packet.hh" 72#include "mem/request.hh" 73#include "params/BaseSimpleCPU.hh" 74#include "sim/byteswap.hh" 75#include "sim/debug.hh" 76#include "sim/sim_events.hh" 77#include "sim/sim_object.hh" 78#include "sim/stats.hh" 79#include "sim/system.hh" 80 |
81using namespace std; 82using namespace TheISA; 83 84BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 85 : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 86{ 87#if FULL_SYSTEM 88 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 89#else 90 thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 91 p->itb, p->dtb); 92#endif // !FULL_SYSTEM 93 94 thread->setStatus(ThreadContext::Halted); 95 96 tc = thread->getTC(); 97 |
98 numInst = 0; 99 startNumInst = 0; 100 numLoad = 0; 101 startNumLoad = 0; 102 lastIcacheStall = 0; 103 lastDcacheStall = 0; 104 105 threadContexts.push_back(tc); 106 107 108 fetchOffset = 0; 109 stayAtPC = false; 110} 111 112BaseSimpleCPU::~BaseSimpleCPU() 113{ 114} 115 116void |
117BaseSimpleCPU::deallocateContext(int thread_num) |
118{ 119 // for now, these are equivalent 120 suspendContext(thread_num); 121} 122 123 124void |
125BaseSimpleCPU::haltContext(int thread_num) |
126{ 127 // for now, these are equivalent 128 suspendContext(thread_num); 129} 130 131 132void 133BaseSimpleCPU::regStats() --- 147 unchanged lines hidden (view full) --- 281 thread->unserialize(cp, csprintf("%s.xc.0", section)); 282} 283 284void 285change_thread_state(ThreadID tid, int activate, int priority) 286{ 287} 288 |
289Addr 290BaseSimpleCPU::dbg_vtophys(Addr addr) 291{ 292 return vtophys(tc, addr); 293} |
294 |
295void 296BaseSimpleCPU::wakeup() 297{ 298 if (thread->status() != ThreadContext::Suspended) 299 return; 300 301 DPRINTF(Quiesce,"Suspended Processor awoke\n"); 302 thread->activate(); 303} |
304 305void 306BaseSimpleCPU::checkForInterrupts() 307{ |
308 if (checkInterrupts(tc)) { 309 Fault interrupt = interrupts->getInterrupt(tc); 310 311 if (interrupt != NoFault) { 312 fetchOffset = 0; 313 interrupts->updateIntrInfo(tc); 314 interrupt->invoke(tc); 315 predecoder.reset(); 316 } 317 } |
318} 319 320 321void 322BaseSimpleCPU::setupFetchRequest(Request *req) 323{ 324 Addr instAddr = thread->instAddr(); 325 --- 81 unchanged lines hidden (view full) --- 407 408void 409BaseSimpleCPU::postExecute() 410{ 411 assert(curStaticInst); 412 413 TheISA::PCState pc = tc->pcState(); 414 Addr instAddr = pc.instAddr(); |
415 if (thread->profile) { 416 bool usermode = TheISA::inUserMode(tc); 417 thread->profilePC = usermode ? 1 : instAddr; 418 ProfileNode *node = thread->profile->consume(tc, curStaticInst); 419 if (node) 420 thread->profileNode = node; 421 } |
422 423 if (curStaticInst->isMemRef()) { 424 numMemRefs++; 425 } 426 427 if (curStaticInst->isLoad()) { 428 ++numLoad; 429 comLoadEventQueue[0]->serviceEvents(numLoad); --- 103 unchanged lines hidden --- |