1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 480 unchanged lines hidden (view full) --- 489 } else { 490 // go to the next instruction 491 thread->setPC(thread->readNextPC()); 492 thread->setNextPC(thread->readNextNPC()); 493 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 494 assert(thread->readNextPC() != thread->readNextNPC()); 495 } 496 } |
497} 498 499/*Fault 500BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 501{ 502 // translate to physical address 503 Fault fault = NoFault; 504 int CacheID = Op & 0x3; // Lower 3 bits identify Cache --- 28 unchanged lines hidden --- |