1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 343 unchanged lines hidden (view full) --- 352BaseSimpleCPU::preExecute() 353{ 354 // maintain $r0 semantics 355 thread->setIntReg(ZeroReg, 0); 356#if THE_ISA == ALPHA_ISA 357 thread->setFloatReg(ZeroReg, 0.0); 358#endif // ALPHA_ISA 359 |
360 // check for instruction-count-based events 361 comInstEventQueue[0]->serviceEvents(numInst); 362 363 // decode the instruction 364 inst = gtoh(inst); 365 366 //If we're not in the middle of a macro instruction 367 if (!curMacroStaticInst) { --- 138 unchanged lines hidden --- |