1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 77 unchanged lines hidden (view full) --- 86 numInst = 0; 87 startNumInst = 0; 88 numLoad = 0; 89 startNumLoad = 0; 90 lastIcacheStall = 0; 91 lastDcacheStall = 0; 92 93 threadContexts.push_back(tc); |
94 95 fetchOffset = 0; 96 stayAtPC = false; |
97} 98 99BaseSimpleCPU::~BaseSimpleCPU() 100{ 101} 102 103void 104BaseSimpleCPU::deallocateContext(int thread_num) --- 228 unchanged lines hidden (view full) --- 333#if ISA_HAS_DELAY_SLOT 334 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(), 335 thread->readNextPC(),thread->readNextNPC()); 336#else 337 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), 338 thread->readNextPC()); 339#endif 340 |
341 const Addr PCMask = ~(sizeof(MachInst) - 1); |
342 Addr fetchPC = thread->readPC() + fetchOffset; 343 req->setVirt(0, fetchPC & PCMask, sizeof(MachInst), 0, thread->readPC()); |
344 345 Fault fault = thread->translateInstReq(req); 346 347 return fault; 348} 349 350 351void --- 11 unchanged lines hidden (view full) --- 363 364 thread->funcExeInst++; 365 366 // check for instruction-count-based events 367 comInstEventQueue[0]->serviceEvents(numInst); 368 369 // decode the instruction 370 inst = gtoh(inst); |
371 |
372 //If we're not in the middle of a macro instruction 373 if (!curMacroStaticInst) { |
374 |
375 StaticInstPtr instPtr = NULL; 376 377 //Predecode, ie bundle up an ExtMachInst 378 //This should go away once the constructor can be set up properly 379 predecoder.setTC(thread->getTC()); 380 //If more fetch data is needed, pass it in. |
381 const Addr PCMask = ~(sizeof(MachInst) - 1); |
382 if(predecoder.needMoreBytes()) |
383 predecoder.moreBytes((thread->readPC() & PCMask) + fetchOffset, 384 0, inst); |
385 else 386 predecoder.process(); |
387 388 //If an instruction is ready, decode it. Otherwise, we'll have to 389 //fetch beyond the MachInst at the current pc. 390 if (predecoder.extMachInstReady()) { 391#if THE_ISA == X86_ISA 392 thread->setNextPC(thread->readPC() + predecoder.getInstSize()); 393#endif // X86_ISA 394 stayAtPC = false; |
395 instPtr = StaticInst::decode(predecoder.getExtMachInst()); |
396 } else { 397 stayAtPC = true; 398 fetchOffset += sizeof(MachInst); 399 } |
400 401 //If we decoded an instruction and it's microcoded, start pulling 402 //out micro ops 403 if (instPtr && instPtr->isMacroOp()) { 404 curMacroStaticInst = instPtr; 405 curStaticInst = curMacroStaticInst-> 406 fetchMicroOp(thread->readMicroPC()); 407 } else { --- 51 unchanged lines hidden (view full) --- 459 traceData = NULL; 460 } 461} 462 463 464void 465BaseSimpleCPU::advancePC(Fault fault) 466{ |
467 //Since we're moving to a new pc, zero out the offset 468 fetchOffset = 0; |
469 if (fault != NoFault) { 470 curMacroStaticInst = StaticInst::nullStaticInstPtr; 471 fault->invoke(tc); 472 thread->setMicroPC(0); 473 thread->setNextMicroPC(1); |
474 } else { |
475 //If we're at the last micro op for this instruction 476 if (curStaticInst && curStaticInst->isLastMicroOp()) { 477 //We should be working with a macro op 478 assert(curMacroStaticInst); 479 //Close out this macro op, and clean up the 480 //microcode state 481 curMacroStaticInst = StaticInst::nullStaticInstPtr; 482 thread->setMicroPC(0); --- 27 unchanged lines hidden --- |