1/* |
2 * Copyright (c) 2010-2012,2015 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 46 unchanged lines hidden (view full) --- 57#include "config/the_isa.hh" 58#include "cpu/simple/base.hh" 59#include "cpu/base.hh" 60#include "cpu/checker/cpu.hh" 61#include "cpu/checker/thread_context.hh" 62#include "cpu/exetrace.hh" 63#include "cpu/pred/bpred_unit.hh" 64#include "cpu/profile.hh" |
65#include "cpu/simple/exec_context.hh" |
66#include "cpu/simple_thread.hh" 67#include "cpu/smt.hh" 68#include "cpu/static_inst.hh" 69#include "cpu/thread_context.hh" 70#include "debug/Decode.hh" 71#include "debug/Fetch.hh" 72#include "debug/Quiesce.hh" 73#include "mem/mem_object.hh" --- 9 unchanged lines hidden (view full) --- 83#include "sim/stats.hh" 84#include "sim/system.hh" 85 86using namespace std; 87using namespace TheISA; 88 89BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 90 : BaseCPU(p), |
91 curThread(0), |
92 branchPred(p->branchPred), |
93 traceData(NULL), 94 inst(), 95 _status(Idle) |
96{ |
97 SimpleThread *thread; |
98 |
99 for (unsigned i = 0; i < numThreads; i++) { 100 if (FullSystem) { 101 thread = new SimpleThread(this, i, p->system, 102 p->itb, p->dtb, p->isa[i]); 103 } else { 104 thread = new SimpleThread(this, i, p->system, p->workload[i], 105 p->itb, p->dtb, p->isa[i]); 106 } 107 threadInfo.push_back(new SimpleExecContext(this, thread)); 108 ThreadContext *tc = thread->getTC(); 109 threadContexts.push_back(tc); 110 } |
111 |
112 if (p->checker) { |
113 if (numThreads != 1) 114 fatal("Checker currently does not support SMT"); 115 |
116 BaseCPU *temp_checker = p->checker; 117 checker = dynamic_cast<CheckerCPU *>(temp_checker); 118 checker->setSystem(p->system); 119 // Manipulate thread context |
120 ThreadContext *cpu_tc = threadContexts[0]; 121 threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); |
122 } else { 123 checker = NULL; 124 } |
125} |
126 |
127void 128BaseSimpleCPU::init() 129{ 130 BaseCPU::init(); |
131 |
132 for (auto tc : threadContexts) { 133 // Initialise the ThreadContext's memory proxies 134 tc->initMemProxies(tc); |
135 |
136 if (FullSystem && !params()->switched_out) { 137 // initialize CPU, including PC 138 TheISA::initCPU(tc, tc->contextId()); 139 } 140 } 141} |
142 |
143void 144BaseSimpleCPU::checkPcEventQueue() 145{ 146 Addr oldpc, pc = threadInfo[curThread]->thread->instAddr(); 147 do { 148 oldpc = pc; 149 system->pcEventQueue.service(threadContexts[curThread]); 150 pc = threadInfo[curThread]->thread->instAddr(); 151 } while (oldpc != pc); |
152} 153 |
154void 155BaseSimpleCPU::swapActiveThread() 156{ 157 if (numThreads > 1) { 158 if ((!curStaticInst || !curStaticInst->isDelayedCommit()) && 159 !threadInfo[curThread]->stayAtPC) { 160 // Swap active threads 161 if (!activeThreads.empty()) { 162 curThread = activeThreads.front(); 163 activeThreads.pop_front(); 164 activeThreads.push_back(curThread); 165 } 166 } 167 } 168} 169 170void 171BaseSimpleCPU::countInst() 172{ 173 SimpleExecContext& t_info = *threadInfo[curThread]; 174 175 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { 176 t_info.numInst++; 177 t_info.numInsts++; 178 } 179 t_info.numOp++; 180 t_info.numOps++; 181 182 system->totalNumInsts++; 183 t_info.thread->funcExeInst++; 184} 185 186Counter 187BaseSimpleCPU::totalInsts() const 188{ 189 Counter total_inst = 0; 190 for (auto& t_info : threadInfo) { 191 total_inst += t_info->numInst; 192 } 193 194 return total_inst; 195} 196 197Counter 198BaseSimpleCPU::totalOps() const 199{ 200 Counter total_op = 0; 201 for (auto& t_info : threadInfo) { 202 total_op += t_info->numOp; 203 } 204 205 return total_op; 206} 207 |
208BaseSimpleCPU::~BaseSimpleCPU() 209{ 210} 211 212void 213BaseSimpleCPU::haltContext(ThreadID thread_num) 214{ 215 // for now, these are equivalent 216 suspendContext(thread_num); 217} 218 219 220void 221BaseSimpleCPU::regStats() 222{ 223 using namespace Stats; 224 225 BaseCPU::regStats(); 226 |
227 for (ThreadID tid = 0; tid < numThreads; tid++) { 228 SimpleExecContext& t_info = *threadInfo[tid]; |
229 |
230 std::string thread_str = name(); 231 if (numThreads > 1) 232 thread_str += ".thread" + std::to_string(tid); |
233 |
234 t_info.numInsts 235 .name(thread_str + ".committedInsts") 236 .desc("Number of instructions committed") 237 ; |
238 |
239 t_info.numOps 240 .name(thread_str + ".committedOps") 241 .desc("Number of ops (including micro ops) committed") 242 ; |
243 |
244 t_info.numIntAluAccesses 245 .name(thread_str + ".num_int_alu_accesses") 246 .desc("Number of integer alu accesses") 247 ; |
248 |
249 t_info.numFpAluAccesses 250 .name(thread_str + ".num_fp_alu_accesses") 251 .desc("Number of float alu accesses") 252 ; |
253 |
254 t_info.numCallsReturns 255 .name(thread_str + ".num_func_calls") 256 .desc("number of times a function call or return occured") 257 ; |
258 |
259 t_info.numCondCtrlInsts 260 .name(thread_str + ".num_conditional_control_insts") 261 .desc("number of instructions that are conditional controls") 262 ; |
263 |
264 t_info.numIntInsts 265 .name(thread_str + ".num_int_insts") 266 .desc("number of integer instructions") 267 ; |
268 |
269 t_info.numFpInsts 270 .name(thread_str + ".num_fp_insts") 271 .desc("number of float instructions") 272 ; |
273 |
274 t_info.numIntRegReads 275 .name(thread_str + ".num_int_register_reads") 276 .desc("number of times the integer registers were read") 277 ; |
278 |
279 t_info.numIntRegWrites 280 .name(thread_str + ".num_int_register_writes") 281 .desc("number of times the integer registers were written") 282 ; |
283 |
284 t_info.numFpRegReads 285 .name(thread_str + ".num_fp_register_reads") 286 .desc("number of times the floating registers were read") 287 ; |
288 |
289 t_info.numFpRegWrites 290 .name(thread_str + ".num_fp_register_writes") 291 .desc("number of times the floating registers were written") 292 ; |
293 |
294 t_info.numCCRegReads 295 .name(thread_str + ".num_cc_register_reads") 296 .desc("number of times the CC registers were read") 297 .flags(nozero) 298 ; |
299 |
300 t_info.numCCRegWrites 301 .name(thread_str + ".num_cc_register_writes") 302 .desc("number of times the CC registers were written") 303 .flags(nozero) 304 ; |
305 |
306 t_info.numMemRefs 307 .name(thread_str + ".num_mem_refs") 308 .desc("number of memory refs") 309 ; |
310 |
311 t_info.numStoreInsts 312 .name(thread_str + ".num_store_insts") 313 .desc("Number of store instructions") 314 ; |
315 |
316 t_info.numLoadInsts 317 .name(thread_str + ".num_load_insts") 318 .desc("Number of load instructions") 319 ; |
320 |
321 t_info.notIdleFraction 322 .name(thread_str + ".not_idle_fraction") 323 .desc("Percentage of non-idle cycles") 324 ; |
325 |
326 t_info.idleFraction 327 .name(thread_str + ".idle_fraction") 328 .desc("Percentage of idle cycles") 329 ; |
330 |
331 t_info.numBusyCycles 332 .name(thread_str + ".num_busy_cycles") 333 .desc("Number of busy cycles") 334 ; |
335 |
336 t_info.numIdleCycles 337 .name(thread_str + ".num_idle_cycles") 338 .desc("Number of idle cycles") 339 ; |
340 |
341 t_info.icacheStallCycles 342 .name(thread_str + ".icache_stall_cycles") 343 .desc("ICache total stall cycles") 344 .prereq(t_info.icacheStallCycles) 345 ; |
346 |
347 t_info.dcacheStallCycles 348 .name(thread_str + ".dcache_stall_cycles") 349 .desc("DCache total stall cycles") 350 .prereq(t_info.dcacheStallCycles) 351 ; |
352 |
353 t_info.statExecutedInstType 354 .init(Enums::Num_OpClass) 355 .name(thread_str + ".op_class") 356 .desc("Class of executed instruction") 357 .flags(total | pdf | dist) 358 ; |
359 |
360 for (unsigned i = 0; i < Num_OpClasses; ++i) { 361 t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]); 362 } |
363 |
364 t_info.idleFraction = constant(1.0) - t_info.notIdleFraction; 365 t_info.numIdleCycles = t_info.idleFraction * numCycles; 366 t_info.numBusyCycles = t_info.notIdleFraction * numCycles; 367 368 t_info.numBranches 369 .name(thread_str + ".Branches") 370 .desc("Number of branches fetched") 371 .prereq(t_info.numBranches); 372 373 t_info.numPredictedBranches 374 .name(thread_str + ".predictedBranches") 375 .desc("Number of branches predicted as taken") 376 .prereq(t_info.numPredictedBranches); 377 378 t_info.numBranchMispred 379 .name(thread_str + ".BranchMispred") 380 .desc("Number of branch mispredictions") 381 .prereq(t_info.numBranchMispred); 382 } |
383} 384 385void 386BaseSimpleCPU::resetStats() 387{ |
388 for (auto &thread_info : threadInfo) { 389 thread_info->notIdleFraction = (_status != Idle); 390 } |
391} 392 393void 394BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const 395{ 396 assert(_status == Idle || _status == Running); |
397 |
398 threadInfo[tid]->thread->serialize(cp); |
399} 400 401void 402BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid) 403{ |
404 threadInfo[tid]->thread->unserialize(cp); |
405} 406 407void 408change_thread_state(ThreadID tid, int activate, int priority) 409{ 410} 411 412Addr 413BaseSimpleCPU::dbg_vtophys(Addr addr) 414{ |
415 return vtophys(threadContexts[curThread], addr); |
416} 417 418void 419BaseSimpleCPU::wakeup() 420{ |
421 getCpuAddrMonitor()->gotWakeup = true; |
422 |
423 for (ThreadID tid = 0; tid < numThreads; tid++) { 424 if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) { 425 DPRINTF(Quiesce,"Suspended Processor awoke\n"); 426 threadInfo[tid]->thread->activate(); 427 } 428 } |
429} 430 431void 432BaseSimpleCPU::checkForInterrupts() 433{ |
434 SimpleExecContext&t_info = *threadInfo[curThread]; 435 SimpleThread* thread = t_info.thread; 436 ThreadContext* tc = thread->getTC(); 437 |
438 if (checkInterrupts(tc)) { 439 Fault interrupt = interrupts->getInterrupt(tc); 440 441 if (interrupt != NoFault) { |
442 t_info.fetchOffset = 0; |
443 interrupts->updateIntrInfo(tc); 444 interrupt->invoke(tc); 445 thread->decoder.reset(); 446 } 447 } 448} 449 450 451void 452BaseSimpleCPU::setupFetchRequest(Request *req) 453{ |
454 SimpleExecContext &t_info = *threadInfo[curThread]; 455 SimpleThread* thread = t_info.thread; 456 |
457 Addr instAddr = thread->instAddr(); 458 459 // set up memory request for instruction fetch 460 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 461 |
462 Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset; |
463 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 464 instAddr); 465} 466 467 468void 469BaseSimpleCPU::preExecute() 470{ |
471 SimpleExecContext &t_info = *threadInfo[curThread]; 472 SimpleThread* thread = t_info.thread; 473 |
474 // maintain $r0 semantics 475 thread->setIntReg(ZeroReg, 0); 476#if THE_ISA == ALPHA_ISA 477 thread->setFloatReg(ZeroReg, 0.0); 478#endif // ALPHA_ISA 479 480 // check for instruction-count-based events |
481 comInstEventQueue[curThread]->serviceEvents(t_info.numInst); |
482 system->instEventQueue.serviceEvents(system->totalNumInsts); 483 484 // decode the instruction 485 inst = gtoh(inst); 486 487 TheISA::PCState pcState = thread->pcState(); 488 489 if (isRomMicroPC(pcState.microPC())) { |
490 t_info.stayAtPC = false; |
491 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 492 curMacroStaticInst); 493 } else if (!curMacroStaticInst) { 494 //We're not in the middle of a macro instruction 495 StaticInstPtr instPtr = NULL; 496 497 TheISA::Decoder *decoder = &(thread->decoder); 498 499 //Predecode, ie bundle up an ExtMachInst 500 //If more fetch data is needed, pass it in. |
501 Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset; |
502 //if(decoder->needMoreBytes()) 503 decoder->moreBytes(pcState, fetchPC, inst); 504 //else 505 // decoder->process(); 506 507 //Decode an instruction if one is ready. Otherwise, we'll have to 508 //fetch beyond the MachInst at the current pc. 509 instPtr = decoder->decode(pcState); 510 if (instPtr) { |
511 t_info.stayAtPC = false; |
512 thread->pcState(pcState); 513 } else { |
514 t_info.stayAtPC = true; 515 t_info.fetchOffset += sizeof(MachInst); |
516 } 517 518 //If we decoded an instruction and it's microcoded, start pulling 519 //out micro ops 520 if (instPtr && instPtr->isMacroop()) { 521 curMacroStaticInst = instPtr; |
522 curStaticInst = 523 curMacroStaticInst->fetchMicroop(pcState.microPC()); |
524 } else { 525 curStaticInst = instPtr; 526 } 527 } else { 528 //Read the next micro op from the macro op 529 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 530 } 531 532 //If we decoded an instruction this "tick", record information about it. 533 if (curStaticInst) { 534#if TRACING_ON |
535 traceData = tracer->getInstRecord(curTick(), thread->getTC(), |
536 curStaticInst, thread->pcState(), curMacroStaticInst); 537 538 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 539 curStaticInst->getName(), curStaticInst->machInst); 540#endif // TRACING_ON 541 } 542 |
543 if (branchPred && curStaticInst && 544 curStaticInst->isControl()) { |
545 // Use a fake sequence number since we only have one 546 // instruction in flight at the same time. 547 const InstSeqNum cur_sn(0); |
548 t_info.predPC = thread->pcState(); |
549 const bool predict_taken( |
550 branchPred->predict(curStaticInst, cur_sn, t_info.predPC, 551 curThread)); |
552 553 if (predict_taken) |
554 ++t_info.numPredictedBranches; |
555 } 556} 557 558void 559BaseSimpleCPU::postExecute() 560{ |
561 SimpleExecContext &t_info = *threadInfo[curThread]; 562 SimpleThread* thread = t_info.thread; 563 |
564 assert(curStaticInst); 565 |
566 TheISA::PCState pc = threadContexts[curThread]->pcState(); |
567 Addr instAddr = pc.instAddr(); 568 if (FullSystem && thread->profile) { |
569 bool usermode = TheISA::inUserMode(threadContexts[curThread]); |
570 thread->profilePC = usermode ? 1 : instAddr; |
571 ProfileNode *node = thread->profile->consume(threadContexts[curThread], 572 curStaticInst); |
573 if (node) 574 thread->profileNode = node; 575 } 576 577 if (curStaticInst->isMemRef()) { |
578 t_info.numMemRefs++; |
579 } 580 581 if (curStaticInst->isLoad()) { |
582 ++t_info.numLoad; 583 comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad); |
584 } 585 586 if (CPA::available()) { |
587 CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr()); |
588 } 589 590 if (curStaticInst->isControl()) { |
591 ++t_info.numBranches; |
592 } 593 594 /* Power model statistics */ 595 //integer alu accesses 596 if (curStaticInst->isInteger()){ |
597 t_info.numIntAluAccesses++; 598 t_info.numIntInsts++; |
599 } 600 601 //float alu accesses 602 if (curStaticInst->isFloating()){ |
603 t_info.numFpAluAccesses++; 604 t_info.numFpInsts++; |
605 } |
606 |
607 //number of function calls/returns to get window accesses 608 if (curStaticInst->isCall() || curStaticInst->isReturn()){ |
609 t_info.numCallsReturns++; |
610 } |
611 |
612 //the number of branch predictions that will be made 613 if (curStaticInst->isCondCtrl()){ |
614 t_info.numCondCtrlInsts++; |
615 } |
616 |
617 //result bus acceses 618 if (curStaticInst->isLoad()){ |
619 t_info.numLoadInsts++; |
620 } |
621 |
622 if (curStaticInst->isStore()){ |
623 t_info.numStoreInsts++; |
624 } 625 /* End power model statistics */ 626 |
627 t_info.statExecutedInstType[curStaticInst->opClass()]++; |
628 629 if (FullSystem) 630 traceFunctions(instAddr); 631 632 if (traceData) { 633 traceData->dump(); 634 delete traceData; 635 traceData = NULL; 636 } 637 638 // Call CPU instruction commit probes 639 probeInstCommit(curStaticInst); 640} 641 642void 643BaseSimpleCPU::advancePC(const Fault &fault) 644{ |
645 SimpleExecContext &t_info = *threadInfo[curThread]; 646 SimpleThread* thread = t_info.thread; 647 |
648 const bool branching(thread->pcState().branching()); 649 650 //Since we're moving to a new pc, zero out the offset |
651 t_info.fetchOffset = 0; |
652 if (fault != NoFault) { 653 curMacroStaticInst = StaticInst::nullStaticInstPtr; |
654 fault->invoke(threadContexts[curThread], curStaticInst); |
655 thread->decoder.reset(); 656 } else { 657 if (curStaticInst) { 658 if (curStaticInst->isLastMicroop()) 659 curMacroStaticInst = StaticInst::nullStaticInstPtr; 660 TheISA::PCState pcState = thread->pcState(); 661 TheISA::advancePC(pcState, curStaticInst); 662 thread->pcState(pcState); 663 } 664 } 665 666 if (branchPred && curStaticInst && curStaticInst->isControl()) { 667 // Use a fake sequence number since we only have one 668 // instruction in flight at the same time. 669 const InstSeqNum cur_sn(0); |
670 |
671 if (t_info.predPC == thread->pcState()) { |
672 // Correctly predicted branch |
673 branchPred->update(cur_sn, curThread); |
674 } else { 675 // Mis-predicted branch |
676 branchPred->squash(cur_sn, thread->pcState(), branching, curThread); 677 ++t_info.numBranchMispred; |
678 } 679 } 680} 681 682void 683BaseSimpleCPU::startup() 684{ 685 BaseCPU::startup(); |
686 for (auto& t_info : threadInfo) 687 t_info->thread->startup(); |
688} |