1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 74 unchanged lines hidden (view full) --- 83#include "sim/system.hh" 84 85using namespace std; 86using namespace TheISA; 87 88BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 89 : BaseCPU(p), 90 branchPred(p->branchPred), |
91 traceData(NULL), thread(NULL), _status(Idle), interval_stats(false), 92 inst() |
93{ 94 if (FullSystem) 95 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb, 96 p->isa[0]); 97 else 98 thread = new SimpleThread(this, /* thread_num */ 0, p->system, 99 p->workload[0], p->itb, p->dtb, p->isa[0]); 100 --- 161 unchanged lines hidden (view full) --- 262 ; 263 264 dcacheStallCycles 265 .name(name() + ".dcache_stall_cycles") 266 .desc("DCache total stall cycles") 267 .prereq(dcacheStallCycles) 268 ; 269 |
270 statExecutedInstType 271 .init(Enums::Num_OpClass) 272 .name(name() + ".op_class") 273 .desc("Class of executed instruction") 274 .flags(total | pdf | dist) 275 ; 276 for (unsigned i = 0; i < Num_OpClasses; ++i) { 277 statExecutedInstType.subname(i, Enums::OpClassStrings[i]); --- 310 unchanged lines hidden --- |