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> #include "cpu/pred/bpred_unit.hh"
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< : BaseCPU(p), traceData(NULL), thread(NULL)
---
> : BaseCPU(p),
> branchPred(p->branchPred),
> traceData(NULL), thread(NULL)
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>
> numBranches
> .name(name() + ".Branches")
> .desc("Number of branches fetched")
> .prereq(numBranches);
>
> numPredictedBranches
> .name(name() + ".predictedBranches")
> .desc("Number of branches predicted as taken")
> .prereq(numPredictedBranches);
>
> numBranchMispred
> .name(name() + ".BranchMispred")
> .desc("Number of branch mispredictions")
> .prereq(numBranchMispred);
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>
> if (branchPred && curStaticInst && curStaticInst->isControl()) {
> // Use a fake sequence number since we only have one
> // instruction in flight at the same time.
> const InstSeqNum cur_sn(0);
> const ThreadID tid(0);
> pred_pc = thread->pcState();
> const bool predict_taken(
> branchPred->predict(curStaticInst, cur_sn, pred_pc, tid));
>
> if (predict_taken)
> ++numPredictedBranches;
> }
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> if (curStaticInst->isControl()) {
> ++numBranches;
> }
>
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<
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> const bool branching(thread->pcState().branching());
>
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>
> if (branchPred && curStaticInst && curStaticInst->isControl()) {
> // Use a fake sequence number since we only have one
> // instruction in flight at the same time.
> const InstSeqNum cur_sn(0);
> const ThreadID tid(0);
>
> if (pred_pc == thread->pcState()) {
> // Correctly predicted branch
> branchPred->update(cur_sn, tid);
> } else {
> // Mis-predicted branch
> branchPred->squash(cur_sn, pcState(),
> branching, tid);
> ++numBranchMispred;
> }
> }