1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/kernel_stats.hh"
44#include "arch/stacktrace.hh"
45#include "arch/tlb.hh"
46#include "arch/utility.hh"
47#include "arch/vtophys.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "base/cprintf.hh"
51#include "base/inifile.hh"
52#include "base/misc.hh"
53#include "base/pollevent.hh"
54#include "base/range.hh"
55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
| 1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/kernel_stats.hh"
44#include "arch/stacktrace.hh"
45#include "arch/tlb.hh"
46#include "arch/utility.hh"
47#include "arch/vtophys.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "base/cprintf.hh"
51#include "base/inifile.hh"
52#include "base/misc.hh"
53#include "base/pollevent.hh"
54#include "base/range.hh"
55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
|
58#include "config/use_checker.hh"
| |
59#include "cpu/simple/base.hh"
60#include "cpu/base.hh"
| 58#include "cpu/simple/base.hh"
59#include "cpu/base.hh"
|
| 60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
|
61#include "cpu/exetrace.hh"
62#include "cpu/profile.hh"
63#include "cpu/simple_thread.hh"
64#include "cpu/smt.hh"
65#include "cpu/static_inst.hh"
66#include "cpu/thread_context.hh"
67#include "debug/Decode.hh"
68#include "debug/Fetch.hh"
69#include "debug/Quiesce.hh"
70#include "mem/mem_object.hh"
71#include "mem/packet.hh"
72#include "mem/request.hh"
73#include "params/BaseSimpleCPU.hh"
74#include "sim/byteswap.hh"
75#include "sim/debug.hh"
76#include "sim/faults.hh"
77#include "sim/full_system.hh"
78#include "sim/sim_events.hh"
79#include "sim/sim_object.hh"
80#include "sim/stats.hh"
81#include "sim/system.hh"
82
| 62#include "cpu/exetrace.hh"
63#include "cpu/profile.hh"
64#include "cpu/simple_thread.hh"
65#include "cpu/smt.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/thread_context.hh"
68#include "debug/Decode.hh"
69#include "debug/Fetch.hh"
70#include "debug/Quiesce.hh"
71#include "mem/mem_object.hh"
72#include "mem/packet.hh"
73#include "mem/request.hh"
74#include "params/BaseSimpleCPU.hh"
75#include "sim/byteswap.hh"
76#include "sim/debug.hh"
77#include "sim/faults.hh"
78#include "sim/full_system.hh"
79#include "sim/sim_events.hh"
80#include "sim/sim_object.hh"
81#include "sim/stats.hh"
82#include "sim/system.hh"
83
|
83#if USE_CHECKER
84#include "cpu/checker/cpu.hh"
85#include "cpu/checker/thread_context.hh"
86#endif
87
| |
88using namespace std;
89using namespace TheISA;
90
91BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
92 : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
93{
94 if (FullSystem)
95 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
96 else
97 thread = new SimpleThread(this, /* thread_num */ 0, p->system,
98 p->workload[0], p->itb, p->dtb);
99
100 thread->setStatus(ThreadContext::Halted);
101
102 tc = thread->getTC();
103
| 84using namespace std;
85using namespace TheISA;
86
87BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
88 : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
89{
90 if (FullSystem)
91 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
92 else
93 thread = new SimpleThread(this, /* thread_num */ 0, p->system,
94 p->workload[0], p->itb, p->dtb);
95
96 thread->setStatus(ThreadContext::Halted);
97
98 tc = thread->getTC();
99
|
104#if USE_CHECKER
| |
105 if (p->checker) {
106 BaseCPU *temp_checker = p->checker;
107 checker = dynamic_cast<CheckerCPU *>(temp_checker);
108 checker->setSystem(p->system);
109 // Manipulate thread context
110 ThreadContext *cpu_tc = tc;
111 tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
112 } else {
113 checker = NULL;
114 }
| 100 if (p->checker) {
101 BaseCPU *temp_checker = p->checker;
102 checker = dynamic_cast<CheckerCPU *>(temp_checker);
103 checker->setSystem(p->system);
104 // Manipulate thread context
105 ThreadContext *cpu_tc = tc;
106 tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
107 } else {
108 checker = NULL;
109 }
|
115#endif
| |
116
117 numInst = 0;
118 startNumInst = 0;
119 numOp = 0;
120 startNumOp = 0;
121 numLoad = 0;
122 startNumLoad = 0;
123 lastIcacheStall = 0;
124 lastDcacheStall = 0;
125
126 threadContexts.push_back(tc);
127
128
129 fetchOffset = 0;
130 stayAtPC = false;
131}
132
133BaseSimpleCPU::~BaseSimpleCPU()
134{
135}
136
137void
138BaseSimpleCPU::deallocateContext(ThreadID thread_num)
139{
140 // for now, these are equivalent
141 suspendContext(thread_num);
142}
143
144
145void
146BaseSimpleCPU::haltContext(ThreadID thread_num)
147{
148 // for now, these are equivalent
149 suspendContext(thread_num);
150}
151
152
153void
154BaseSimpleCPU::regStats()
155{
156 using namespace Stats;
157
158 BaseCPU::regStats();
159
160 numInsts
161 .name(name() + ".committedInsts")
162 .desc("Number of instructions committed")
163 ;
164
165 numOps
166 .name(name() + ".committedOps")
167 .desc("Number of ops (including micro ops) committed")
168 ;
169
170 numIntAluAccesses
171 .name(name() + ".num_int_alu_accesses")
172 .desc("Number of integer alu accesses")
173 ;
174
175 numFpAluAccesses
176 .name(name() + ".num_fp_alu_accesses")
177 .desc("Number of float alu accesses")
178 ;
179
180 numCallsReturns
181 .name(name() + ".num_func_calls")
182 .desc("number of times a function call or return occured")
183 ;
184
185 numCondCtrlInsts
186 .name(name() + ".num_conditional_control_insts")
187 .desc("number of instructions that are conditional controls")
188 ;
189
190 numIntInsts
191 .name(name() + ".num_int_insts")
192 .desc("number of integer instructions")
193 ;
194
195 numFpInsts
196 .name(name() + ".num_fp_insts")
197 .desc("number of float instructions")
198 ;
199
200 numIntRegReads
201 .name(name() + ".num_int_register_reads")
202 .desc("number of times the integer registers were read")
203 ;
204
205 numIntRegWrites
206 .name(name() + ".num_int_register_writes")
207 .desc("number of times the integer registers were written")
208 ;
209
210 numFpRegReads
211 .name(name() + ".num_fp_register_reads")
212 .desc("number of times the floating registers were read")
213 ;
214
215 numFpRegWrites
216 .name(name() + ".num_fp_register_writes")
217 .desc("number of times the floating registers were written")
218 ;
219
220 numMemRefs
221 .name(name()+".num_mem_refs")
222 .desc("number of memory refs")
223 ;
224
225 numStoreInsts
226 .name(name() + ".num_store_insts")
227 .desc("Number of store instructions")
228 ;
229
230 numLoadInsts
231 .name(name() + ".num_load_insts")
232 .desc("Number of load instructions")
233 ;
234
235 notIdleFraction
236 .name(name() + ".not_idle_fraction")
237 .desc("Percentage of non-idle cycles")
238 ;
239
240 idleFraction
241 .name(name() + ".idle_fraction")
242 .desc("Percentage of idle cycles")
243 ;
244
245 numBusyCycles
246 .name(name() + ".num_busy_cycles")
247 .desc("Number of busy cycles")
248 ;
249
250 numIdleCycles
251 .name(name()+".num_idle_cycles")
252 .desc("Number of idle cycles")
253 ;
254
255 icacheStallCycles
256 .name(name() + ".icache_stall_cycles")
257 .desc("ICache total stall cycles")
258 .prereq(icacheStallCycles)
259 ;
260
261 dcacheStallCycles
262 .name(name() + ".dcache_stall_cycles")
263 .desc("DCache total stall cycles")
264 .prereq(dcacheStallCycles)
265 ;
266
267 icacheRetryCycles
268 .name(name() + ".icache_retry_cycles")
269 .desc("ICache total retry cycles")
270 .prereq(icacheRetryCycles)
271 ;
272
273 dcacheRetryCycles
274 .name(name() + ".dcache_retry_cycles")
275 .desc("DCache total retry cycles")
276 .prereq(dcacheRetryCycles)
277 ;
278
279 idleFraction = constant(1.0) - notIdleFraction;
280 numIdleCycles = idleFraction * numCycles;
281 numBusyCycles = (notIdleFraction)*numCycles;
282}
283
284void
285BaseSimpleCPU::resetStats()
286{
287// startNumInst = numInst;
288 notIdleFraction = (_status != Idle);
289}
290
291void
292BaseSimpleCPU::serialize(ostream &os)
293{
294 SERIALIZE_ENUM(_status);
295 BaseCPU::serialize(os);
296// SERIALIZE_SCALAR(inst);
297 nameOut(os, csprintf("%s.xc.0", name()));
298 thread->serialize(os);
299}
300
301void
302BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
303{
304 UNSERIALIZE_ENUM(_status);
305 BaseCPU::unserialize(cp, section);
306// UNSERIALIZE_SCALAR(inst);
307 thread->unserialize(cp, csprintf("%s.xc.0", section));
308}
309
310void
311change_thread_state(ThreadID tid, int activate, int priority)
312{
313}
314
315Addr
316BaseSimpleCPU::dbg_vtophys(Addr addr)
317{
318 return vtophys(tc, addr);
319}
320
321void
322BaseSimpleCPU::wakeup()
323{
324 if (thread->status() != ThreadContext::Suspended)
325 return;
326
327 DPRINTF(Quiesce,"Suspended Processor awoke\n");
328 thread->activate();
329}
330
331void
332BaseSimpleCPU::checkForInterrupts()
333{
334 if (checkInterrupts(tc)) {
335 Fault interrupt = interrupts->getInterrupt(tc);
336
337 if (interrupt != NoFault) {
338 fetchOffset = 0;
339 interrupts->updateIntrInfo(tc);
340 interrupt->invoke(tc);
341 predecoder.reset();
342 }
343 }
344}
345
346
347void
348BaseSimpleCPU::setupFetchRequest(Request *req)
349{
350 Addr instAddr = thread->instAddr();
351
352 // set up memory request for instruction fetch
353 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
354
355 Addr fetchPC = (instAddr & PCMask) + fetchOffset;
356 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
357 instAddr);
358}
359
360
361void
362BaseSimpleCPU::preExecute()
363{
364 // maintain $r0 semantics
365 thread->setIntReg(ZeroReg, 0);
366#if THE_ISA == ALPHA_ISA
367 thread->setFloatReg(ZeroReg, 0.0);
368#endif // ALPHA_ISA
369
370 // check for instruction-count-based events
371 comInstEventQueue[0]->serviceEvents(numInst);
372 system->instEventQueue.serviceEvents(system->totalNumInsts);
373
374 // decode the instruction
375 inst = gtoh(inst);
376
377 TheISA::PCState pcState = thread->pcState();
378
379 if (isRomMicroPC(pcState.microPC())) {
380 stayAtPC = false;
381 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
382 curMacroStaticInst);
383 } else if (!curMacroStaticInst) {
384 //We're not in the middle of a macro instruction
385 StaticInstPtr instPtr = NULL;
386
387 //Predecode, ie bundle up an ExtMachInst
388 //This should go away once the constructor can be set up properly
389 predecoder.setTC(thread->getTC());
390 //If more fetch data is needed, pass it in.
391 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
392 //if(predecoder.needMoreBytes())
393 predecoder.moreBytes(pcState, fetchPC, inst);
394 //else
395 // predecoder.process();
396
397 //If an instruction is ready, decode it. Otherwise, we'll have to
398 //fetch beyond the MachInst at the current pc.
399 if (predecoder.extMachInstReady()) {
400 stayAtPC = false;
401 ExtMachInst machInst = predecoder.getExtMachInst(pcState);
402 thread->pcState(pcState);
403 instPtr = thread->decoder.decode(machInst, pcState.instAddr());
404 } else {
405 stayAtPC = true;
406 fetchOffset += sizeof(MachInst);
407 }
408
409 //If we decoded an instruction and it's microcoded, start pulling
410 //out micro ops
411 if (instPtr && instPtr->isMacroop()) {
412 curMacroStaticInst = instPtr;
413 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
414 } else {
415 curStaticInst = instPtr;
416 }
417 } else {
418 //Read the next micro op from the macro op
419 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
420 }
421
422 //If we decoded an instruction this "tick", record information about it.
423 if(curStaticInst)
424 {
425#if TRACING_ON
426 traceData = tracer->getInstRecord(curTick(), tc,
427 curStaticInst, thread->pcState(), curMacroStaticInst);
428
429 DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
430 curStaticInst->getName(), curStaticInst->machInst);
431#endif // TRACING_ON
432 }
433}
434
435void
436BaseSimpleCPU::postExecute()
437{
438 assert(curStaticInst);
439
440 TheISA::PCState pc = tc->pcState();
441 Addr instAddr = pc.instAddr();
442 if (FullSystem && thread->profile) {
443 bool usermode = TheISA::inUserMode(tc);
444 thread->profilePC = usermode ? 1 : instAddr;
445 ProfileNode *node = thread->profile->consume(tc, curStaticInst);
446 if (node)
447 thread->profileNode = node;
448 }
449
450 if (curStaticInst->isMemRef()) {
451 numMemRefs++;
452 }
453
454 if (curStaticInst->isLoad()) {
455 ++numLoad;
456 comLoadEventQueue[0]->serviceEvents(numLoad);
457 }
458
459 if (CPA::available()) {
460 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
461 }
462
463 /* Power model statistics */
464 //integer alu accesses
465 if (curStaticInst->isInteger()){
466 numIntAluAccesses++;
467 numIntInsts++;
468 }
469
470 //float alu accesses
471 if (curStaticInst->isFloating()){
472 numFpAluAccesses++;
473 numFpInsts++;
474 }
475
476 //number of function calls/returns to get window accesses
477 if (curStaticInst->isCall() || curStaticInst->isReturn()){
478 numCallsReturns++;
479 }
480
481 //the number of branch predictions that will be made
482 if (curStaticInst->isCondCtrl()){
483 numCondCtrlInsts++;
484 }
485
486 //result bus acceses
487 if (curStaticInst->isLoad()){
488 numLoadInsts++;
489 }
490
491 if (curStaticInst->isStore()){
492 numStoreInsts++;
493 }
494 /* End power model statistics */
495
496 if (FullSystem)
497 traceFunctions(instAddr);
498
499 if (traceData) {
500 traceData->dump();
501 delete traceData;
502 traceData = NULL;
503 }
504}
505
506
507void
508BaseSimpleCPU::advancePC(Fault fault)
509{
510 //Since we're moving to a new pc, zero out the offset
511 fetchOffset = 0;
512 if (fault != NoFault) {
513 curMacroStaticInst = StaticInst::nullStaticInstPtr;
514 fault->invoke(tc, curStaticInst);
515 predecoder.reset();
516 } else {
517 if (curStaticInst) {
518 if (curStaticInst->isLastMicroop())
519 curMacroStaticInst = StaticInst::nullStaticInstPtr;
520 TheISA::PCState pcState = thread->pcState();
521 TheISA::advancePC(pcState, curStaticInst);
522 thread->pcState(pcState);
523 }
524 }
525}
526
527/*Fault
528BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
529{
530 // translate to physical address
531 Fault fault = NoFault;
532 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
533 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
534 if(CacheID > 1)
535 {
536 warn("CacheOps not implemented for secondary/tertiary caches\n");
537 }
538 else
539 {
540 switch(CacheOP)
541 { // Fill Packet Type
542 case 0: warn("Invalidate Cache Op\n");
543 break;
544 case 1: warn("Index Load Tag Cache Op\n");
545 break;
546 case 2: warn("Index Store Tag Cache Op\n");
547 break;
548 case 4: warn("Hit Invalidate Cache Op\n");
549 break;
550 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
551 break;
552 case 6: warn("Hit Writeback\n");
553 break;
554 case 7: warn("Fetch & Lock Cache Op\n");
555 break;
556 default: warn("Unimplemented Cache Op\n");
557 }
558 }
559 return fault;
560}*/
| 110
111 numInst = 0;
112 startNumInst = 0;
113 numOp = 0;
114 startNumOp = 0;
115 numLoad = 0;
116 startNumLoad = 0;
117 lastIcacheStall = 0;
118 lastDcacheStall = 0;
119
120 threadContexts.push_back(tc);
121
122
123 fetchOffset = 0;
124 stayAtPC = false;
125}
126
127BaseSimpleCPU::~BaseSimpleCPU()
128{
129}
130
131void
132BaseSimpleCPU::deallocateContext(ThreadID thread_num)
133{
134 // for now, these are equivalent
135 suspendContext(thread_num);
136}
137
138
139void
140BaseSimpleCPU::haltContext(ThreadID thread_num)
141{
142 // for now, these are equivalent
143 suspendContext(thread_num);
144}
145
146
147void
148BaseSimpleCPU::regStats()
149{
150 using namespace Stats;
151
152 BaseCPU::regStats();
153
154 numInsts
155 .name(name() + ".committedInsts")
156 .desc("Number of instructions committed")
157 ;
158
159 numOps
160 .name(name() + ".committedOps")
161 .desc("Number of ops (including micro ops) committed")
162 ;
163
164 numIntAluAccesses
165 .name(name() + ".num_int_alu_accesses")
166 .desc("Number of integer alu accesses")
167 ;
168
169 numFpAluAccesses
170 .name(name() + ".num_fp_alu_accesses")
171 .desc("Number of float alu accesses")
172 ;
173
174 numCallsReturns
175 .name(name() + ".num_func_calls")
176 .desc("number of times a function call or return occured")
177 ;
178
179 numCondCtrlInsts
180 .name(name() + ".num_conditional_control_insts")
181 .desc("number of instructions that are conditional controls")
182 ;
183
184 numIntInsts
185 .name(name() + ".num_int_insts")
186 .desc("number of integer instructions")
187 ;
188
189 numFpInsts
190 .name(name() + ".num_fp_insts")
191 .desc("number of float instructions")
192 ;
193
194 numIntRegReads
195 .name(name() + ".num_int_register_reads")
196 .desc("number of times the integer registers were read")
197 ;
198
199 numIntRegWrites
200 .name(name() + ".num_int_register_writes")
201 .desc("number of times the integer registers were written")
202 ;
203
204 numFpRegReads
205 .name(name() + ".num_fp_register_reads")
206 .desc("number of times the floating registers were read")
207 ;
208
209 numFpRegWrites
210 .name(name() + ".num_fp_register_writes")
211 .desc("number of times the floating registers were written")
212 ;
213
214 numMemRefs
215 .name(name()+".num_mem_refs")
216 .desc("number of memory refs")
217 ;
218
219 numStoreInsts
220 .name(name() + ".num_store_insts")
221 .desc("Number of store instructions")
222 ;
223
224 numLoadInsts
225 .name(name() + ".num_load_insts")
226 .desc("Number of load instructions")
227 ;
228
229 notIdleFraction
230 .name(name() + ".not_idle_fraction")
231 .desc("Percentage of non-idle cycles")
232 ;
233
234 idleFraction
235 .name(name() + ".idle_fraction")
236 .desc("Percentage of idle cycles")
237 ;
238
239 numBusyCycles
240 .name(name() + ".num_busy_cycles")
241 .desc("Number of busy cycles")
242 ;
243
244 numIdleCycles
245 .name(name()+".num_idle_cycles")
246 .desc("Number of idle cycles")
247 ;
248
249 icacheStallCycles
250 .name(name() + ".icache_stall_cycles")
251 .desc("ICache total stall cycles")
252 .prereq(icacheStallCycles)
253 ;
254
255 dcacheStallCycles
256 .name(name() + ".dcache_stall_cycles")
257 .desc("DCache total stall cycles")
258 .prereq(dcacheStallCycles)
259 ;
260
261 icacheRetryCycles
262 .name(name() + ".icache_retry_cycles")
263 .desc("ICache total retry cycles")
264 .prereq(icacheRetryCycles)
265 ;
266
267 dcacheRetryCycles
268 .name(name() + ".dcache_retry_cycles")
269 .desc("DCache total retry cycles")
270 .prereq(dcacheRetryCycles)
271 ;
272
273 idleFraction = constant(1.0) - notIdleFraction;
274 numIdleCycles = idleFraction * numCycles;
275 numBusyCycles = (notIdleFraction)*numCycles;
276}
277
278void
279BaseSimpleCPU::resetStats()
280{
281// startNumInst = numInst;
282 notIdleFraction = (_status != Idle);
283}
284
285void
286BaseSimpleCPU::serialize(ostream &os)
287{
288 SERIALIZE_ENUM(_status);
289 BaseCPU::serialize(os);
290// SERIALIZE_SCALAR(inst);
291 nameOut(os, csprintf("%s.xc.0", name()));
292 thread->serialize(os);
293}
294
295void
296BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
297{
298 UNSERIALIZE_ENUM(_status);
299 BaseCPU::unserialize(cp, section);
300// UNSERIALIZE_SCALAR(inst);
301 thread->unserialize(cp, csprintf("%s.xc.0", section));
302}
303
304void
305change_thread_state(ThreadID tid, int activate, int priority)
306{
307}
308
309Addr
310BaseSimpleCPU::dbg_vtophys(Addr addr)
311{
312 return vtophys(tc, addr);
313}
314
315void
316BaseSimpleCPU::wakeup()
317{
318 if (thread->status() != ThreadContext::Suspended)
319 return;
320
321 DPRINTF(Quiesce,"Suspended Processor awoke\n");
322 thread->activate();
323}
324
325void
326BaseSimpleCPU::checkForInterrupts()
327{
328 if (checkInterrupts(tc)) {
329 Fault interrupt = interrupts->getInterrupt(tc);
330
331 if (interrupt != NoFault) {
332 fetchOffset = 0;
333 interrupts->updateIntrInfo(tc);
334 interrupt->invoke(tc);
335 predecoder.reset();
336 }
337 }
338}
339
340
341void
342BaseSimpleCPU::setupFetchRequest(Request *req)
343{
344 Addr instAddr = thread->instAddr();
345
346 // set up memory request for instruction fetch
347 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
348
349 Addr fetchPC = (instAddr & PCMask) + fetchOffset;
350 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
351 instAddr);
352}
353
354
355void
356BaseSimpleCPU::preExecute()
357{
358 // maintain $r0 semantics
359 thread->setIntReg(ZeroReg, 0);
360#if THE_ISA == ALPHA_ISA
361 thread->setFloatReg(ZeroReg, 0.0);
362#endif // ALPHA_ISA
363
364 // check for instruction-count-based events
365 comInstEventQueue[0]->serviceEvents(numInst);
366 system->instEventQueue.serviceEvents(system->totalNumInsts);
367
368 // decode the instruction
369 inst = gtoh(inst);
370
371 TheISA::PCState pcState = thread->pcState();
372
373 if (isRomMicroPC(pcState.microPC())) {
374 stayAtPC = false;
375 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
376 curMacroStaticInst);
377 } else if (!curMacroStaticInst) {
378 //We're not in the middle of a macro instruction
379 StaticInstPtr instPtr = NULL;
380
381 //Predecode, ie bundle up an ExtMachInst
382 //This should go away once the constructor can be set up properly
383 predecoder.setTC(thread->getTC());
384 //If more fetch data is needed, pass it in.
385 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
386 //if(predecoder.needMoreBytes())
387 predecoder.moreBytes(pcState, fetchPC, inst);
388 //else
389 // predecoder.process();
390
391 //If an instruction is ready, decode it. Otherwise, we'll have to
392 //fetch beyond the MachInst at the current pc.
393 if (predecoder.extMachInstReady()) {
394 stayAtPC = false;
395 ExtMachInst machInst = predecoder.getExtMachInst(pcState);
396 thread->pcState(pcState);
397 instPtr = thread->decoder.decode(machInst, pcState.instAddr());
398 } else {
399 stayAtPC = true;
400 fetchOffset += sizeof(MachInst);
401 }
402
403 //If we decoded an instruction and it's microcoded, start pulling
404 //out micro ops
405 if (instPtr && instPtr->isMacroop()) {
406 curMacroStaticInst = instPtr;
407 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
408 } else {
409 curStaticInst = instPtr;
410 }
411 } else {
412 //Read the next micro op from the macro op
413 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
414 }
415
416 //If we decoded an instruction this "tick", record information about it.
417 if(curStaticInst)
418 {
419#if TRACING_ON
420 traceData = tracer->getInstRecord(curTick(), tc,
421 curStaticInst, thread->pcState(), curMacroStaticInst);
422
423 DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
424 curStaticInst->getName(), curStaticInst->machInst);
425#endif // TRACING_ON
426 }
427}
428
429void
430BaseSimpleCPU::postExecute()
431{
432 assert(curStaticInst);
433
434 TheISA::PCState pc = tc->pcState();
435 Addr instAddr = pc.instAddr();
436 if (FullSystem && thread->profile) {
437 bool usermode = TheISA::inUserMode(tc);
438 thread->profilePC = usermode ? 1 : instAddr;
439 ProfileNode *node = thread->profile->consume(tc, curStaticInst);
440 if (node)
441 thread->profileNode = node;
442 }
443
444 if (curStaticInst->isMemRef()) {
445 numMemRefs++;
446 }
447
448 if (curStaticInst->isLoad()) {
449 ++numLoad;
450 comLoadEventQueue[0]->serviceEvents(numLoad);
451 }
452
453 if (CPA::available()) {
454 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
455 }
456
457 /* Power model statistics */
458 //integer alu accesses
459 if (curStaticInst->isInteger()){
460 numIntAluAccesses++;
461 numIntInsts++;
462 }
463
464 //float alu accesses
465 if (curStaticInst->isFloating()){
466 numFpAluAccesses++;
467 numFpInsts++;
468 }
469
470 //number of function calls/returns to get window accesses
471 if (curStaticInst->isCall() || curStaticInst->isReturn()){
472 numCallsReturns++;
473 }
474
475 //the number of branch predictions that will be made
476 if (curStaticInst->isCondCtrl()){
477 numCondCtrlInsts++;
478 }
479
480 //result bus acceses
481 if (curStaticInst->isLoad()){
482 numLoadInsts++;
483 }
484
485 if (curStaticInst->isStore()){
486 numStoreInsts++;
487 }
488 /* End power model statistics */
489
490 if (FullSystem)
491 traceFunctions(instAddr);
492
493 if (traceData) {
494 traceData->dump();
495 delete traceData;
496 traceData = NULL;
497 }
498}
499
500
501void
502BaseSimpleCPU::advancePC(Fault fault)
503{
504 //Since we're moving to a new pc, zero out the offset
505 fetchOffset = 0;
506 if (fault != NoFault) {
507 curMacroStaticInst = StaticInst::nullStaticInstPtr;
508 fault->invoke(tc, curStaticInst);
509 predecoder.reset();
510 } else {
511 if (curStaticInst) {
512 if (curStaticInst->isLastMicroop())
513 curMacroStaticInst = StaticInst::nullStaticInstPtr;
514 TheISA::PCState pcState = thread->pcState();
515 TheISA::advancePC(pcState, curStaticInst);
516 thread->pcState(pcState);
517 }
518 }
519}
520
521/*Fault
522BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
523{
524 // translate to physical address
525 Fault fault = NoFault;
526 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
527 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
528 if(CacheID > 1)
529 {
530 warn("CacheOps not implemented for secondary/tertiary caches\n");
531 }
532 else
533 {
534 switch(CacheOP)
535 { // Fill Packet Type
536 case 0: warn("Invalidate Cache Op\n");
537 break;
538 case 1: warn("Index Load Tag Cache Op\n");
539 break;
540 case 2: warn("Index Store Tag Cache Op\n");
541 break;
542 case 4: warn("Hit Invalidate Cache Op\n");
543 break;
544 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
545 break;
546 case 6: warn("Hit Writeback\n");
547 break;
548 case 7: warn("Fetch & Lock Cache Op\n");
549 break;
550 default: warn("Unimplemented Cache Op\n");
551 }
552 }
553 return fault;
554}*/
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