base.cc (6331:d947798df4a1) base.cc (6429:7ed8937e375a)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/faults.hh"
32#include "arch/utility.hh"
33#include "base/cp_annotate.hh"
34#include "base/cprintf.hh"
35#include "base/inifile.hh"
36#include "base/loader/symtab.hh"
37#include "base/misc.hh"
38#include "base/pollevent.hh"
39#include "base/range.hh"
40#include "base/stats/events.hh"
41#include "base/trace.hh"
42#include "base/types.hh"
43#include "cpu/base.hh"
44#include "cpu/exetrace.hh"
45#include "cpu/profile.hh"
46#include "cpu/simple/base.hh"
47#include "cpu/simple_thread.hh"
48#include "cpu/smt.hh"
49#include "cpu/static_inst.hh"
50#include "cpu/thread_context.hh"
51#include "mem/packet.hh"
52#include "mem/request.hh"
53#include "params/BaseSimpleCPU.hh"
54#include "sim/byteswap.hh"
55#include "sim/debug.hh"
56#include "sim/sim_events.hh"
57#include "sim/sim_object.hh"
58#include "sim/stats.hh"
59#include "sim/system.hh"
60
61#if FULL_SYSTEM
62#include "arch/kernel_stats.hh"
63#include "arch/stacktrace.hh"
64#include "arch/tlb.hh"
65#include "arch/vtophys.hh"
66#include "base/remote_gdb.hh"
67#else // !FULL_SYSTEM
68#include "mem/mem_object.hh"
69#endif // FULL_SYSTEM
70
71using namespace std;
72using namespace TheISA;
73
74BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
75 : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
76{
77#if FULL_SYSTEM
78 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
79#else
80 thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
81 p->itb, p->dtb);
82#endif // !FULL_SYSTEM
83
84 thread->setStatus(ThreadContext::Halted);
85
86 tc = thread->getTC();
87
88 numInst = 0;
89 startNumInst = 0;
90 numLoad = 0;
91 startNumLoad = 0;
92 lastIcacheStall = 0;
93 lastDcacheStall = 0;
94
95 threadContexts.push_back(tc);
96
97
98 fetchOffset = 0;
99 stayAtPC = false;
100}
101
102BaseSimpleCPU::~BaseSimpleCPU()
103{
104}
105
106void
107BaseSimpleCPU::deallocateContext(int thread_num)
108{
109 // for now, these are equivalent
110 suspendContext(thread_num);
111}
112
113
114void
115BaseSimpleCPU::haltContext(int thread_num)
116{
117 // for now, these are equivalent
118 suspendContext(thread_num);
119}
120
121
122void
123BaseSimpleCPU::regStats()
124{
125 using namespace Stats;
126
127 BaseCPU::regStats();
128
129 numInsts
130 .name(name() + ".num_insts")
131 .desc("Number of instructions executed")
132 ;
133
134 numMemRefs
135 .name(name() + ".num_refs")
136 .desc("Number of memory references")
137 ;
138
139 notIdleFraction
140 .name(name() + ".not_idle_fraction")
141 .desc("Percentage of non-idle cycles")
142 ;
143
144 idleFraction
145 .name(name() + ".idle_fraction")
146 .desc("Percentage of idle cycles")
147 ;
148
149 icacheStallCycles
150 .name(name() + ".icache_stall_cycles")
151 .desc("ICache total stall cycles")
152 .prereq(icacheStallCycles)
153 ;
154
155 dcacheStallCycles
156 .name(name() + ".dcache_stall_cycles")
157 .desc("DCache total stall cycles")
158 .prereq(dcacheStallCycles)
159 ;
160
161 icacheRetryCycles
162 .name(name() + ".icache_retry_cycles")
163 .desc("ICache total retry cycles")
164 .prereq(icacheRetryCycles)
165 ;
166
167 dcacheRetryCycles
168 .name(name() + ".dcache_retry_cycles")
169 .desc("DCache total retry cycles")
170 .prereq(dcacheRetryCycles)
171 ;
172
173 idleFraction = constant(1.0) - notIdleFraction;
174}
175
176void
177BaseSimpleCPU::resetStats()
178{
179// startNumInst = numInst;
180 notIdleFraction = (_status != Idle);
181}
182
183void
184BaseSimpleCPU::serialize(ostream &os)
185{
186 SERIALIZE_ENUM(_status);
187 BaseCPU::serialize(os);
188// SERIALIZE_SCALAR(inst);
189 nameOut(os, csprintf("%s.xc.0", name()));
190 thread->serialize(os);
191}
192
193void
194BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
195{
196 UNSERIALIZE_ENUM(_status);
197 BaseCPU::unserialize(cp, section);
198// UNSERIALIZE_SCALAR(inst);
199 thread->unserialize(cp, csprintf("%s.xc.0", section));
200}
201
202void
203change_thread_state(ThreadID tid, int activate, int priority)
204{
205}
206
207Fault
208BaseSimpleCPU::copySrcTranslate(Addr src)
209{
210#if 0
211 static bool no_warn = true;
212 unsigned blk_size =
213 (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
214 // Only support block sizes of 64 atm.
215 assert(blk_size == 64);
216 int offset = src & (blk_size - 1);
217
218 // Make sure block doesn't span page
219 if (no_warn &&
220 (src & PageMask) != ((src + blk_size) & PageMask) &&
221 (src >> 40) != 0xfffffc) {
222 warn("Copied block source spans pages %x.", src);
223 no_warn = false;
224 }
225
226 memReq->reset(src & ~(blk_size - 1), blk_size);
227
228 // translate to physical address
229 Fault fault = thread->translateDataReadReq(req);
230
231 if (fault == NoFault) {
232 thread->copySrcAddr = src;
233 thread->copySrcPhysAddr = memReq->paddr + offset;
234 } else {
235 assert(!fault->isAlignmentFault());
236
237 thread->copySrcAddr = 0;
238 thread->copySrcPhysAddr = 0;
239 }
240 return fault;
241#else
242 return NoFault;
243#endif
244}
245
246Fault
247BaseSimpleCPU::copy(Addr dest)
248{
249#if 0
250 static bool no_warn = true;
251 unsigned blk_size =
252 (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
253 // Only support block sizes of 64 atm.
254 assert(blk_size == 64);
255 uint8_t data[blk_size];
256 //assert(thread->copySrcAddr);
257 int offset = dest & (blk_size - 1);
258
259 // Make sure block doesn't span page
260 if (no_warn &&
261 (dest & PageMask) != ((dest + blk_size) & PageMask) &&
262 (dest >> 40) != 0xfffffc) {
263 no_warn = false;
264 warn("Copied block destination spans pages %x. ", dest);
265 }
266
267 memReq->reset(dest & ~(blk_size -1), blk_size);
268 // translate to physical address
269 Fault fault = thread->translateDataWriteReq(req);
270
271 if (fault == NoFault) {
272 Addr dest_addr = memReq->paddr + offset;
273 // Need to read straight from memory since we have more than 8 bytes.
274 memReq->paddr = thread->copySrcPhysAddr;
275 thread->mem->read(memReq, data);
276 memReq->paddr = dest_addr;
277 thread->mem->write(memReq, data);
278 if (dcacheInterface) {
279 memReq->cmd = Copy;
280 memReq->completionEvent = NULL;
281 memReq->paddr = thread->copySrcPhysAddr;
282 memReq->dest = dest_addr;
283 memReq->size = 64;
284 memReq->time = curTick;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/faults.hh"
32#include "arch/utility.hh"
33#include "base/cp_annotate.hh"
34#include "base/cprintf.hh"
35#include "base/inifile.hh"
36#include "base/loader/symtab.hh"
37#include "base/misc.hh"
38#include "base/pollevent.hh"
39#include "base/range.hh"
40#include "base/stats/events.hh"
41#include "base/trace.hh"
42#include "base/types.hh"
43#include "cpu/base.hh"
44#include "cpu/exetrace.hh"
45#include "cpu/profile.hh"
46#include "cpu/simple/base.hh"
47#include "cpu/simple_thread.hh"
48#include "cpu/smt.hh"
49#include "cpu/static_inst.hh"
50#include "cpu/thread_context.hh"
51#include "mem/packet.hh"
52#include "mem/request.hh"
53#include "params/BaseSimpleCPU.hh"
54#include "sim/byteswap.hh"
55#include "sim/debug.hh"
56#include "sim/sim_events.hh"
57#include "sim/sim_object.hh"
58#include "sim/stats.hh"
59#include "sim/system.hh"
60
61#if FULL_SYSTEM
62#include "arch/kernel_stats.hh"
63#include "arch/stacktrace.hh"
64#include "arch/tlb.hh"
65#include "arch/vtophys.hh"
66#include "base/remote_gdb.hh"
67#else // !FULL_SYSTEM
68#include "mem/mem_object.hh"
69#endif // FULL_SYSTEM
70
71using namespace std;
72using namespace TheISA;
73
74BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
75 : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
76{
77#if FULL_SYSTEM
78 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
79#else
80 thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
81 p->itb, p->dtb);
82#endif // !FULL_SYSTEM
83
84 thread->setStatus(ThreadContext::Halted);
85
86 tc = thread->getTC();
87
88 numInst = 0;
89 startNumInst = 0;
90 numLoad = 0;
91 startNumLoad = 0;
92 lastIcacheStall = 0;
93 lastDcacheStall = 0;
94
95 threadContexts.push_back(tc);
96
97
98 fetchOffset = 0;
99 stayAtPC = false;
100}
101
102BaseSimpleCPU::~BaseSimpleCPU()
103{
104}
105
106void
107BaseSimpleCPU::deallocateContext(int thread_num)
108{
109 // for now, these are equivalent
110 suspendContext(thread_num);
111}
112
113
114void
115BaseSimpleCPU::haltContext(int thread_num)
116{
117 // for now, these are equivalent
118 suspendContext(thread_num);
119}
120
121
122void
123BaseSimpleCPU::regStats()
124{
125 using namespace Stats;
126
127 BaseCPU::regStats();
128
129 numInsts
130 .name(name() + ".num_insts")
131 .desc("Number of instructions executed")
132 ;
133
134 numMemRefs
135 .name(name() + ".num_refs")
136 .desc("Number of memory references")
137 ;
138
139 notIdleFraction
140 .name(name() + ".not_idle_fraction")
141 .desc("Percentage of non-idle cycles")
142 ;
143
144 idleFraction
145 .name(name() + ".idle_fraction")
146 .desc("Percentage of idle cycles")
147 ;
148
149 icacheStallCycles
150 .name(name() + ".icache_stall_cycles")
151 .desc("ICache total stall cycles")
152 .prereq(icacheStallCycles)
153 ;
154
155 dcacheStallCycles
156 .name(name() + ".dcache_stall_cycles")
157 .desc("DCache total stall cycles")
158 .prereq(dcacheStallCycles)
159 ;
160
161 icacheRetryCycles
162 .name(name() + ".icache_retry_cycles")
163 .desc("ICache total retry cycles")
164 .prereq(icacheRetryCycles)
165 ;
166
167 dcacheRetryCycles
168 .name(name() + ".dcache_retry_cycles")
169 .desc("DCache total retry cycles")
170 .prereq(dcacheRetryCycles)
171 ;
172
173 idleFraction = constant(1.0) - notIdleFraction;
174}
175
176void
177BaseSimpleCPU::resetStats()
178{
179// startNumInst = numInst;
180 notIdleFraction = (_status != Idle);
181}
182
183void
184BaseSimpleCPU::serialize(ostream &os)
185{
186 SERIALIZE_ENUM(_status);
187 BaseCPU::serialize(os);
188// SERIALIZE_SCALAR(inst);
189 nameOut(os, csprintf("%s.xc.0", name()));
190 thread->serialize(os);
191}
192
193void
194BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
195{
196 UNSERIALIZE_ENUM(_status);
197 BaseCPU::unserialize(cp, section);
198// UNSERIALIZE_SCALAR(inst);
199 thread->unserialize(cp, csprintf("%s.xc.0", section));
200}
201
202void
203change_thread_state(ThreadID tid, int activate, int priority)
204{
205}
206
207Fault
208BaseSimpleCPU::copySrcTranslate(Addr src)
209{
210#if 0
211 static bool no_warn = true;
212 unsigned blk_size =
213 (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
214 // Only support block sizes of 64 atm.
215 assert(blk_size == 64);
216 int offset = src & (blk_size - 1);
217
218 // Make sure block doesn't span page
219 if (no_warn &&
220 (src & PageMask) != ((src + blk_size) & PageMask) &&
221 (src >> 40) != 0xfffffc) {
222 warn("Copied block source spans pages %x.", src);
223 no_warn = false;
224 }
225
226 memReq->reset(src & ~(blk_size - 1), blk_size);
227
228 // translate to physical address
229 Fault fault = thread->translateDataReadReq(req);
230
231 if (fault == NoFault) {
232 thread->copySrcAddr = src;
233 thread->copySrcPhysAddr = memReq->paddr + offset;
234 } else {
235 assert(!fault->isAlignmentFault());
236
237 thread->copySrcAddr = 0;
238 thread->copySrcPhysAddr = 0;
239 }
240 return fault;
241#else
242 return NoFault;
243#endif
244}
245
246Fault
247BaseSimpleCPU::copy(Addr dest)
248{
249#if 0
250 static bool no_warn = true;
251 unsigned blk_size =
252 (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
253 // Only support block sizes of 64 atm.
254 assert(blk_size == 64);
255 uint8_t data[blk_size];
256 //assert(thread->copySrcAddr);
257 int offset = dest & (blk_size - 1);
258
259 // Make sure block doesn't span page
260 if (no_warn &&
261 (dest & PageMask) != ((dest + blk_size) & PageMask) &&
262 (dest >> 40) != 0xfffffc) {
263 no_warn = false;
264 warn("Copied block destination spans pages %x. ", dest);
265 }
266
267 memReq->reset(dest & ~(blk_size -1), blk_size);
268 // translate to physical address
269 Fault fault = thread->translateDataWriteReq(req);
270
271 if (fault == NoFault) {
272 Addr dest_addr = memReq->paddr + offset;
273 // Need to read straight from memory since we have more than 8 bytes.
274 memReq->paddr = thread->copySrcPhysAddr;
275 thread->mem->read(memReq, data);
276 memReq->paddr = dest_addr;
277 thread->mem->write(memReq, data);
278 if (dcacheInterface) {
279 memReq->cmd = Copy;
280 memReq->completionEvent = NULL;
281 memReq->paddr = thread->copySrcPhysAddr;
282 memReq->dest = dest_addr;
283 memReq->size = 64;
284 memReq->time = curTick;
285 memReq->flags &= ~INST_FETCH;
286 dcacheInterface->access(memReq);
287 }
288 }
289 else
290 assert(!fault->isAlignmentFault());
291
292 return fault;
293#else
294 panic("copy not implemented");
295 return NoFault;
296#endif
297}
298
299#if FULL_SYSTEM
300Addr
301BaseSimpleCPU::dbg_vtophys(Addr addr)
302{
303 return vtophys(tc, addr);
304}
305#endif // FULL_SYSTEM
306
307#if FULL_SYSTEM
308void
309BaseSimpleCPU::wakeup()
310{
311 if (thread->status() != ThreadContext::Suspended)
312 return;
313
314 DPRINTF(Quiesce,"Suspended Processor awoke\n");
315 thread->activate();
316}
317#endif // FULL_SYSTEM
318
319void
320BaseSimpleCPU::checkForInterrupts()
321{
322#if FULL_SYSTEM
323 if (checkInterrupts(tc)) {
324 Fault interrupt = interrupts->getInterrupt(tc);
325
326 if (interrupt != NoFault) {
327 predecoder.reset();
328 interrupts->updateIntrInfo(tc);
329 interrupt->invoke(tc);
330 }
331 }
332#endif
333}
334
335
336void
337BaseSimpleCPU::setupFetchRequest(Request *req)
338{
339 Addr threadPC = thread->readPC();
340
341 // set up memory request for instruction fetch
342#if ISA_HAS_DELAY_SLOT
343 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
344 thread->readNextPC(),thread->readNextNPC());
345#else
346 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
347 thread->readNextPC());
348#endif
349
350 Addr fetchPC = (threadPC & PCMask) + fetchOffset;
351 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC);
352}
353
354
355void
356BaseSimpleCPU::preExecute()
357{
358 // maintain $r0 semantics
359 thread->setIntReg(ZeroReg, 0);
360#if THE_ISA == ALPHA_ISA
361 thread->setFloatReg(ZeroReg, 0.0);
362#endif // ALPHA_ISA
363
364 // check for instruction-count-based events
365 comInstEventQueue[0]->serviceEvents(numInst);
366
367 // decode the instruction
368 inst = gtoh(inst);
369
370 MicroPC upc = thread->readMicroPC();
371
372 if (isRomMicroPC(upc)) {
373 stayAtPC = false;
374 curStaticInst = microcodeRom.fetchMicroop(upc, curMacroStaticInst);
375 } else if (!curMacroStaticInst) {
376 //We're not in the middle of a macro instruction
377 StaticInstPtr instPtr = NULL;
378
379 //Predecode, ie bundle up an ExtMachInst
380 //This should go away once the constructor can be set up properly
381 predecoder.setTC(thread->getTC());
382 //If more fetch data is needed, pass it in.
383 Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
384 //if(predecoder.needMoreBytes())
385 predecoder.moreBytes(thread->readPC(), fetchPC, inst);
386 //else
387 // predecoder.process();
388
389 //If an instruction is ready, decode it. Otherwise, we'll have to
390 //fetch beyond the MachInst at the current pc.
391 if (predecoder.extMachInstReady()) {
392#if THE_ISA == X86_ISA
393 thread->setNextPC(thread->readPC() + predecoder.getInstSize());
394#endif // X86_ISA
395 stayAtPC = false;
396 instPtr = StaticInst::decode(predecoder.getExtMachInst(),
397 thread->readPC());
398 } else {
399 stayAtPC = true;
400 fetchOffset += sizeof(MachInst);
401 }
402
403 //If we decoded an instruction and it's microcoded, start pulling
404 //out micro ops
405 if (instPtr && instPtr->isMacroop()) {
406 curMacroStaticInst = instPtr;
407 curStaticInst = curMacroStaticInst->fetchMicroop(upc);
408 } else {
409 curStaticInst = instPtr;
410 }
411 } else {
412 //Read the next micro op from the macro op
413 curStaticInst = curMacroStaticInst->fetchMicroop(upc);
414 }
415
416 //If we decoded an instruction this "tick", record information about it.
417 if(curStaticInst)
418 {
419#if TRACING_ON
420 traceData = tracer->getInstRecord(curTick, tc,
421 curStaticInst, thread->readPC(),
422 curMacroStaticInst, thread->readMicroPC());
423
424 DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
425 curStaticInst->getName(), curStaticInst->machInst);
426#endif // TRACING_ON
427
428#if FULL_SYSTEM
429 thread->setInst(inst);
430#endif // FULL_SYSTEM
431 }
432}
433
434void
435BaseSimpleCPU::postExecute()
436{
437#if FULL_SYSTEM
438 if (thread->profile && curStaticInst) {
439 bool usermode = TheISA::inUserMode(tc);
440 thread->profilePC = usermode ? 1 : thread->readPC();
441 ProfileNode *node = thread->profile->consume(tc, curStaticInst);
442 if (node)
443 thread->profileNode = node;
444 }
445#endif
446
447 if (curStaticInst->isMemRef()) {
448 numMemRefs++;
449 }
450
451 if (curStaticInst->isLoad()) {
452 ++numLoad;
453 comLoadEventQueue[0]->serviceEvents(numLoad);
454 }
455
456 if (CPA::available()) {
457 CPA::cpa()->swAutoBegin(tc, thread->readNextPC());
458 }
459
460 traceFunctions(thread->readPC());
461
462 if (traceData) {
463 traceData->dump();
464 delete traceData;
465 traceData = NULL;
466 }
467}
468
469
470void
471BaseSimpleCPU::advancePC(Fault fault)
472{
473 //Since we're moving to a new pc, zero out the offset
474 fetchOffset = 0;
475 if (fault != NoFault) {
476 curMacroStaticInst = StaticInst::nullStaticInstPtr;
477 predecoder.reset();
478 fault->invoke(tc);
479 } else {
480 //If we're at the last micro op for this instruction
481 if (curStaticInst && curStaticInst->isLastMicroop()) {
482 //We should be working with a macro op or be in the ROM
483 assert(curMacroStaticInst ||
484 isRomMicroPC(thread->readMicroPC()));
485 //Close out this macro op, and clean up the
486 //microcode state
487 curMacroStaticInst = StaticInst::nullStaticInstPtr;
488 thread->setMicroPC(normalMicroPC(0));
489 thread->setNextMicroPC(normalMicroPC(1));
490 }
491 //If we're still in a macro op
492 if (curMacroStaticInst || isRomMicroPC(thread->readMicroPC())) {
493 //Advance the micro pc
494 thread->setMicroPC(thread->readNextMicroPC());
495 //Advance the "next" micro pc. Note that there are no delay
496 //slots, and micro ops are "word" addressed.
497 thread->setNextMicroPC(thread->readNextMicroPC() + 1);
498 } else {
499 // go to the next instruction
500 thread->setPC(thread->readNextPC());
501 thread->setNextPC(thread->readNextNPC());
502 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
503 assert(thread->readNextPC() != thread->readNextNPC());
504 }
505 }
506}
507
508/*Fault
509BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
510{
511 // translate to physical address
512 Fault fault = NoFault;
513 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
514 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
515 if(CacheID > 1)
516 {
517 warn("CacheOps not implemented for secondary/tertiary caches\n");
518 }
519 else
520 {
521 switch(CacheOP)
522 { // Fill Packet Type
523 case 0: warn("Invalidate Cache Op\n");
524 break;
525 case 1: warn("Index Load Tag Cache Op\n");
526 break;
527 case 2: warn("Index Store Tag Cache Op\n");
528 break;
529 case 4: warn("Hit Invalidate Cache Op\n");
530 break;
531 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
532 break;
533 case 6: warn("Hit Writeback\n");
534 break;
535 case 7: warn("Fetch & Lock Cache Op\n");
536 break;
537 default: warn("Unimplemented Cache Op\n");
538 }
539 }
540 return fault;
541}*/
285 dcacheInterface->access(memReq);
286 }
287 }
288 else
289 assert(!fault->isAlignmentFault());
290
291 return fault;
292#else
293 panic("copy not implemented");
294 return NoFault;
295#endif
296}
297
298#if FULL_SYSTEM
299Addr
300BaseSimpleCPU::dbg_vtophys(Addr addr)
301{
302 return vtophys(tc, addr);
303}
304#endif // FULL_SYSTEM
305
306#if FULL_SYSTEM
307void
308BaseSimpleCPU::wakeup()
309{
310 if (thread->status() != ThreadContext::Suspended)
311 return;
312
313 DPRINTF(Quiesce,"Suspended Processor awoke\n");
314 thread->activate();
315}
316#endif // FULL_SYSTEM
317
318void
319BaseSimpleCPU::checkForInterrupts()
320{
321#if FULL_SYSTEM
322 if (checkInterrupts(tc)) {
323 Fault interrupt = interrupts->getInterrupt(tc);
324
325 if (interrupt != NoFault) {
326 predecoder.reset();
327 interrupts->updateIntrInfo(tc);
328 interrupt->invoke(tc);
329 }
330 }
331#endif
332}
333
334
335void
336BaseSimpleCPU::setupFetchRequest(Request *req)
337{
338 Addr threadPC = thread->readPC();
339
340 // set up memory request for instruction fetch
341#if ISA_HAS_DELAY_SLOT
342 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
343 thread->readNextPC(),thread->readNextNPC());
344#else
345 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
346 thread->readNextPC());
347#endif
348
349 Addr fetchPC = (threadPC & PCMask) + fetchOffset;
350 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC);
351}
352
353
354void
355BaseSimpleCPU::preExecute()
356{
357 // maintain $r0 semantics
358 thread->setIntReg(ZeroReg, 0);
359#if THE_ISA == ALPHA_ISA
360 thread->setFloatReg(ZeroReg, 0.0);
361#endif // ALPHA_ISA
362
363 // check for instruction-count-based events
364 comInstEventQueue[0]->serviceEvents(numInst);
365
366 // decode the instruction
367 inst = gtoh(inst);
368
369 MicroPC upc = thread->readMicroPC();
370
371 if (isRomMicroPC(upc)) {
372 stayAtPC = false;
373 curStaticInst = microcodeRom.fetchMicroop(upc, curMacroStaticInst);
374 } else if (!curMacroStaticInst) {
375 //We're not in the middle of a macro instruction
376 StaticInstPtr instPtr = NULL;
377
378 //Predecode, ie bundle up an ExtMachInst
379 //This should go away once the constructor can be set up properly
380 predecoder.setTC(thread->getTC());
381 //If more fetch data is needed, pass it in.
382 Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
383 //if(predecoder.needMoreBytes())
384 predecoder.moreBytes(thread->readPC(), fetchPC, inst);
385 //else
386 // predecoder.process();
387
388 //If an instruction is ready, decode it. Otherwise, we'll have to
389 //fetch beyond the MachInst at the current pc.
390 if (predecoder.extMachInstReady()) {
391#if THE_ISA == X86_ISA
392 thread->setNextPC(thread->readPC() + predecoder.getInstSize());
393#endif // X86_ISA
394 stayAtPC = false;
395 instPtr = StaticInst::decode(predecoder.getExtMachInst(),
396 thread->readPC());
397 } else {
398 stayAtPC = true;
399 fetchOffset += sizeof(MachInst);
400 }
401
402 //If we decoded an instruction and it's microcoded, start pulling
403 //out micro ops
404 if (instPtr && instPtr->isMacroop()) {
405 curMacroStaticInst = instPtr;
406 curStaticInst = curMacroStaticInst->fetchMicroop(upc);
407 } else {
408 curStaticInst = instPtr;
409 }
410 } else {
411 //Read the next micro op from the macro op
412 curStaticInst = curMacroStaticInst->fetchMicroop(upc);
413 }
414
415 //If we decoded an instruction this "tick", record information about it.
416 if(curStaticInst)
417 {
418#if TRACING_ON
419 traceData = tracer->getInstRecord(curTick, tc,
420 curStaticInst, thread->readPC(),
421 curMacroStaticInst, thread->readMicroPC());
422
423 DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
424 curStaticInst->getName(), curStaticInst->machInst);
425#endif // TRACING_ON
426
427#if FULL_SYSTEM
428 thread->setInst(inst);
429#endif // FULL_SYSTEM
430 }
431}
432
433void
434BaseSimpleCPU::postExecute()
435{
436#if FULL_SYSTEM
437 if (thread->profile && curStaticInst) {
438 bool usermode = TheISA::inUserMode(tc);
439 thread->profilePC = usermode ? 1 : thread->readPC();
440 ProfileNode *node = thread->profile->consume(tc, curStaticInst);
441 if (node)
442 thread->profileNode = node;
443 }
444#endif
445
446 if (curStaticInst->isMemRef()) {
447 numMemRefs++;
448 }
449
450 if (curStaticInst->isLoad()) {
451 ++numLoad;
452 comLoadEventQueue[0]->serviceEvents(numLoad);
453 }
454
455 if (CPA::available()) {
456 CPA::cpa()->swAutoBegin(tc, thread->readNextPC());
457 }
458
459 traceFunctions(thread->readPC());
460
461 if (traceData) {
462 traceData->dump();
463 delete traceData;
464 traceData = NULL;
465 }
466}
467
468
469void
470BaseSimpleCPU::advancePC(Fault fault)
471{
472 //Since we're moving to a new pc, zero out the offset
473 fetchOffset = 0;
474 if (fault != NoFault) {
475 curMacroStaticInst = StaticInst::nullStaticInstPtr;
476 predecoder.reset();
477 fault->invoke(tc);
478 } else {
479 //If we're at the last micro op for this instruction
480 if (curStaticInst && curStaticInst->isLastMicroop()) {
481 //We should be working with a macro op or be in the ROM
482 assert(curMacroStaticInst ||
483 isRomMicroPC(thread->readMicroPC()));
484 //Close out this macro op, and clean up the
485 //microcode state
486 curMacroStaticInst = StaticInst::nullStaticInstPtr;
487 thread->setMicroPC(normalMicroPC(0));
488 thread->setNextMicroPC(normalMicroPC(1));
489 }
490 //If we're still in a macro op
491 if (curMacroStaticInst || isRomMicroPC(thread->readMicroPC())) {
492 //Advance the micro pc
493 thread->setMicroPC(thread->readNextMicroPC());
494 //Advance the "next" micro pc. Note that there are no delay
495 //slots, and micro ops are "word" addressed.
496 thread->setNextMicroPC(thread->readNextMicroPC() + 1);
497 } else {
498 // go to the next instruction
499 thread->setPC(thread->readNextPC());
500 thread->setNextPC(thread->readNextNPC());
501 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
502 assert(thread->readNextPC() != thread->readNextNPC());
503 }
504 }
505}
506
507/*Fault
508BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
509{
510 // translate to physical address
511 Fault fault = NoFault;
512 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
513 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
514 if(CacheID > 1)
515 {
516 warn("CacheOps not implemented for secondary/tertiary caches\n");
517 }
518 else
519 {
520 switch(CacheOP)
521 { // Fill Packet Type
522 case 0: warn("Invalidate Cache Op\n");
523 break;
524 case 1: warn("Index Load Tag Cache Op\n");
525 break;
526 case 2: warn("Index Store Tag Cache Op\n");
527 break;
528 case 4: warn("Hit Invalidate Cache Op\n");
529 break;
530 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
531 break;
532 case 6: warn("Hit Writeback\n");
533 break;
534 case 7: warn("Fetch & Lock Cache Op\n");
535 break;
536 default: warn("Unimplemented Cache Op\n");
537 }
538 }
539 return fault;
540}*/