1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
|
30 */
31
32#include "arch/utility.hh"
33#include "base/cprintf.hh"
34#include "base/inifile.hh"
35#include "base/loader/symtab.hh"
36#include "base/misc.hh"
37#include "base/pollevent.hh"
38#include "base/range.hh"
39#include "base/stats/events.hh"
40#include "base/trace.hh"
41#include "cpu/base.hh"
42#include "cpu/exetrace.hh"
43#include "cpu/profile.hh"
44#include "cpu/simple/base.hh"
45#include "cpu/simple_thread.hh"
46#include "cpu/smt.hh"
47#include "cpu/static_inst.hh"
48#include "cpu/thread_context.hh"
49#include "kern/kernel_stats.hh"
50#include "mem/packet_impl.hh"
51#include "sim/builder.hh"
52#include "sim/byteswap.hh"
53#include "sim/debug.hh"
54#include "sim/host.hh"
55#include "sim/sim_events.hh"
56#include "sim/sim_object.hh"
57#include "sim/stats.hh"
58#include "sim/system.hh"
59
60#if FULL_SYSTEM
61#include "base/remote_gdb.hh"
62#include "arch/tlb.hh"
63#include "arch/stacktrace.hh"
64#include "arch/vtophys.hh"
65#else // !FULL_SYSTEM
66#include "mem/mem_object.hh"
67#endif // FULL_SYSTEM
68
69using namespace std;
70using namespace TheISA;
71
72BaseSimpleCPU::BaseSimpleCPU(Params *p)
73 : BaseCPU(p), mem(p->mem), thread(NULL)
74{
75#if FULL_SYSTEM
76 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
77#else
78 thread = new SimpleThread(this, /* thread_num */ 0, p->process,
79 /* asid */ 0, mem);
80#endif // !FULL_SYSTEM
81
82 thread->setStatus(ThreadContext::Suspended);
83
84 tc = thread->getTC();
85
86 numInst = 0;
87 startNumInst = 0;
88 numLoad = 0;
89 startNumLoad = 0;
90 lastIcacheStall = 0;
91 lastDcacheStall = 0;
92
93 threadContexts.push_back(tc);
94}
95
96BaseSimpleCPU::~BaseSimpleCPU()
97{
98}
99
100void
101BaseSimpleCPU::deallocateContext(int thread_num)
102{
103 // for now, these are equivalent
104 suspendContext(thread_num);
105}
106
107
108void
109BaseSimpleCPU::haltContext(int thread_num)
110{
111 // for now, these are equivalent
112 suspendContext(thread_num);
113}
114
115
116void
117BaseSimpleCPU::regStats()
118{
119 using namespace Stats;
120
121 BaseCPU::regStats();
122
123 numInsts
124 .name(name() + ".num_insts")
125 .desc("Number of instructions executed")
126 ;
127
128 numMemRefs
129 .name(name() + ".num_refs")
130 .desc("Number of memory references")
131 ;
132
133 notIdleFraction
134 .name(name() + ".not_idle_fraction")
135 .desc("Percentage of non-idle cycles")
136 ;
137
138 idleFraction
139 .name(name() + ".idle_fraction")
140 .desc("Percentage of idle cycles")
141 ;
142
143 icacheStallCycles
144 .name(name() + ".icache_stall_cycles")
145 .desc("ICache total stall cycles")
146 .prereq(icacheStallCycles)
147 ;
148
149 dcacheStallCycles
150 .name(name() + ".dcache_stall_cycles")
151 .desc("DCache total stall cycles")
152 .prereq(dcacheStallCycles)
153 ;
154
155 icacheRetryCycles
156 .name(name() + ".icache_retry_cycles")
157 .desc("ICache total retry cycles")
158 .prereq(icacheRetryCycles)
159 ;
160
161 dcacheRetryCycles
162 .name(name() + ".dcache_retry_cycles")
163 .desc("DCache total retry cycles")
164 .prereq(dcacheRetryCycles)
165 ;
166
167 idleFraction = constant(1.0) - notIdleFraction;
168}
169
170void
171BaseSimpleCPU::resetStats()
172{
173 startNumInst = numInst;
174 // notIdleFraction = (_status != Idle);
175}
176
177void
178BaseSimpleCPU::serialize(ostream &os)
179{
180 BaseCPU::serialize(os);
181// SERIALIZE_SCALAR(inst);
182 nameOut(os, csprintf("%s.xc.0", name()));
183 thread->serialize(os);
184}
185
186void
187BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
188{
189 BaseCPU::unserialize(cp, section);
190// UNSERIALIZE_SCALAR(inst);
191 thread->unserialize(cp, csprintf("%s.xc.0", section));
192}
193
194void
195change_thread_state(int thread_number, int activate, int priority)
196{
197}
198
199Fault
200BaseSimpleCPU::copySrcTranslate(Addr src)
201{
202#if 0
203 static bool no_warn = true;
204 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
205 // Only support block sizes of 64 atm.
206 assert(blk_size == 64);
207 int offset = src & (blk_size - 1);
208
209 // Make sure block doesn't span page
210 if (no_warn &&
211 (src & PageMask) != ((src + blk_size) & PageMask) &&
212 (src >> 40) != 0xfffffc) {
213 warn("Copied block source spans pages %x.", src);
214 no_warn = false;
215 }
216
217 memReq->reset(src & ~(blk_size - 1), blk_size);
218
219 // translate to physical address
220 Fault fault = thread->translateDataReadReq(req);
221
222 if (fault == NoFault) {
223 thread->copySrcAddr = src;
224 thread->copySrcPhysAddr = memReq->paddr + offset;
225 } else {
226 assert(!fault->isAlignmentFault());
227
228 thread->copySrcAddr = 0;
229 thread->copySrcPhysAddr = 0;
230 }
231 return fault;
232#else
233 return NoFault;
234#endif
235}
236
237Fault
238BaseSimpleCPU::copy(Addr dest)
239{
240#if 0
241 static bool no_warn = true;
242 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
243 // Only support block sizes of 64 atm.
244 assert(blk_size == 64);
245 uint8_t data[blk_size];
246 //assert(thread->copySrcAddr);
247 int offset = dest & (blk_size - 1);
248
249 // Make sure block doesn't span page
250 if (no_warn &&
251 (dest & PageMask) != ((dest + blk_size) & PageMask) &&
252 (dest >> 40) != 0xfffffc) {
253 no_warn = false;
254 warn("Copied block destination spans pages %x. ", dest);
255 }
256
257 memReq->reset(dest & ~(blk_size -1), blk_size);
258 // translate to physical address
259 Fault fault = thread->translateDataWriteReq(req);
260
261 if (fault == NoFault) {
262 Addr dest_addr = memReq->paddr + offset;
263 // Need to read straight from memory since we have more than 8 bytes.
264 memReq->paddr = thread->copySrcPhysAddr;
265 thread->mem->read(memReq, data);
266 memReq->paddr = dest_addr;
267 thread->mem->write(memReq, data);
268 if (dcacheInterface) {
269 memReq->cmd = Copy;
270 memReq->completionEvent = NULL;
271 memReq->paddr = thread->copySrcPhysAddr;
272 memReq->dest = dest_addr;
273 memReq->size = 64;
274 memReq->time = curTick;
275 memReq->flags &= ~INST_READ;
276 dcacheInterface->access(memReq);
277 }
278 }
279 else
280 assert(!fault->isAlignmentFault());
281
282 return fault;
283#else
284 panic("copy not implemented");
285 return NoFault;
286#endif
287}
288
289#if FULL_SYSTEM
290Addr
291BaseSimpleCPU::dbg_vtophys(Addr addr)
292{
293 return vtophys(tc, addr);
294}
295#endif // FULL_SYSTEM
296
297#if FULL_SYSTEM
298void
299BaseSimpleCPU::post_interrupt(int int_num, int index)
300{
301 BaseCPU::post_interrupt(int_num, index);
302
303 if (thread->status() == ThreadContext::Suspended) {
304 DPRINTF(IPI,"Suspended Processor awoke\n");
305 thread->activate();
306 }
307}
308#endif // FULL_SYSTEM
309
310void
311BaseSimpleCPU::checkForInterrupts()
312{
313#if FULL_SYSTEM
314 if (checkInterrupts && check_interrupts() && !thread->inPalMode()) {
315 int ipl = 0;
316 int summary = 0;
317 checkInterrupts = false;
318
319 if (thread->readMiscReg(IPR_SIRR)) {
320 for (int i = INTLEVEL_SOFTWARE_MIN;
321 i < INTLEVEL_SOFTWARE_MAX; i++) {
322 if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
323 // See table 4-19 of 21164 hardware reference
324 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
325 summary |= (ULL(1) << i);
326 }
327 }
328 }
329
330 uint64_t interrupts = thread->cpu->intr_status();
331 for (int i = INTLEVEL_EXTERNAL_MIN;
332 i < INTLEVEL_EXTERNAL_MAX; i++) {
333 if (interrupts & (ULL(1) << i)) {
334 // See table 4-19 of 21164 hardware reference
335 ipl = i;
336 summary |= (ULL(1) << i);
337 }
338 }
339
340 if (thread->readMiscReg(IPR_ASTRR))
341 panic("asynchronous traps not implemented\n");
342
343 if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
344 thread->setMiscReg(IPR_ISR, summary);
345 thread->setMiscReg(IPR_INTID, ipl);
346
347 Fault(new InterruptFault)->invoke(tc);
348
349 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
350 thread->readMiscReg(IPR_IPLR), ipl, summary);
351 }
352 }
353#endif
354}
355
356
357Fault
358BaseSimpleCPU::setupFetchRequest(Request *req)
359{
360 // set up memory request for instruction fetch
361#if THE_ISA == ALPHA_ISA
362 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
363 thread->readNextPC());
364#else
365 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
366 thread->readNextPC(),thread->readNextNPC());
367#endif
368
369 req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
370 (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0,
371 thread->readPC());
372
373 Fault fault = thread->translateInstReq(req);
374
375 return fault;
376}
377
378
379void
380BaseSimpleCPU::preExecute()
381{
382 // maintain $r0 semantics
383 thread->setIntReg(ZeroReg, 0);
384#if THE_ISA == ALPHA_ISA
385 thread->setFloatReg(ZeroReg, 0.0);
386#endif // ALPHA_ISA
387
388 // keep an instruction count
389 numInst++;
390 numInsts++;
391
392 thread->funcExeInst++;
393
394 // check for instruction-count-based events
395 comInstEventQueue[0]->serviceEvents(numInst);
396
397 // decode the instruction
398 inst = gtoh(inst);
399 curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC()));
400
401 traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst,
402 thread->readPC());
403
404 DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
405 curStaticInst->getName(), curStaticInst->getOpcode(),
406 curStaticInst->machInst);
407
408#if FULL_SYSTEM
409 thread->setInst(inst);
410#endif // FULL_SYSTEM
411}
412
413void
414BaseSimpleCPU::postExecute()
415{
416#if FULL_SYSTEM
417 if (thread->profile) {
418 bool usermode =
419 (thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
420 thread->profilePC = usermode ? 1 : thread->readPC();
421 ProfileNode *node = thread->profile->consume(tc, inst);
422 if (node)
423 thread->profileNode = node;
424 }
425#endif
426
427 if (curStaticInst->isMemRef()) {
428 numMemRefs++;
429 }
430
431 if (curStaticInst->isLoad()) {
432 ++numLoad;
433 comLoadEventQueue[0]->serviceEvents(numLoad);
434 }
435
436 traceFunctions(thread->readPC());
437
438 if (traceData) {
439 traceData->finalize();
440 }
441}
442
443
444void
445BaseSimpleCPU::advancePC(Fault fault)
446{
447 if (fault != NoFault) {
448 fault->invoke(tc);
449 }
450 else {
451 // go to the next instruction
452 thread->setPC(thread->readNextPC());
453#if THE_ISA == ALPHA_ISA
454 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
455#else
456 thread->setNextPC(thread->readNextNPC());
457 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
| 29 */
30
31#include "arch/utility.hh"
32#include "base/cprintf.hh"
33#include "base/inifile.hh"
34#include "base/loader/symtab.hh"
35#include "base/misc.hh"
36#include "base/pollevent.hh"
37#include "base/range.hh"
38#include "base/stats/events.hh"
39#include "base/trace.hh"
40#include "cpu/base.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/profile.hh"
43#include "cpu/simple/base.hh"
44#include "cpu/simple_thread.hh"
45#include "cpu/smt.hh"
46#include "cpu/static_inst.hh"
47#include "cpu/thread_context.hh"
48#include "kern/kernel_stats.hh"
49#include "mem/packet_impl.hh"
50#include "sim/builder.hh"
51#include "sim/byteswap.hh"
52#include "sim/debug.hh"
53#include "sim/host.hh"
54#include "sim/sim_events.hh"
55#include "sim/sim_object.hh"
56#include "sim/stats.hh"
57#include "sim/system.hh"
58
59#if FULL_SYSTEM
60#include "base/remote_gdb.hh"
61#include "arch/tlb.hh"
62#include "arch/stacktrace.hh"
63#include "arch/vtophys.hh"
64#else // !FULL_SYSTEM
65#include "mem/mem_object.hh"
66#endif // FULL_SYSTEM
67
68using namespace std;
69using namespace TheISA;
70
71BaseSimpleCPU::BaseSimpleCPU(Params *p)
72 : BaseCPU(p), mem(p->mem), thread(NULL)
73{
74#if FULL_SYSTEM
75 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
76#else
77 thread = new SimpleThread(this, /* thread_num */ 0, p->process,
78 /* asid */ 0, mem);
79#endif // !FULL_SYSTEM
80
81 thread->setStatus(ThreadContext::Suspended);
82
83 tc = thread->getTC();
84
85 numInst = 0;
86 startNumInst = 0;
87 numLoad = 0;
88 startNumLoad = 0;
89 lastIcacheStall = 0;
90 lastDcacheStall = 0;
91
92 threadContexts.push_back(tc);
93}
94
95BaseSimpleCPU::~BaseSimpleCPU()
96{
97}
98
99void
100BaseSimpleCPU::deallocateContext(int thread_num)
101{
102 // for now, these are equivalent
103 suspendContext(thread_num);
104}
105
106
107void
108BaseSimpleCPU::haltContext(int thread_num)
109{
110 // for now, these are equivalent
111 suspendContext(thread_num);
112}
113
114
115void
116BaseSimpleCPU::regStats()
117{
118 using namespace Stats;
119
120 BaseCPU::regStats();
121
122 numInsts
123 .name(name() + ".num_insts")
124 .desc("Number of instructions executed")
125 ;
126
127 numMemRefs
128 .name(name() + ".num_refs")
129 .desc("Number of memory references")
130 ;
131
132 notIdleFraction
133 .name(name() + ".not_idle_fraction")
134 .desc("Percentage of non-idle cycles")
135 ;
136
137 idleFraction
138 .name(name() + ".idle_fraction")
139 .desc("Percentage of idle cycles")
140 ;
141
142 icacheStallCycles
143 .name(name() + ".icache_stall_cycles")
144 .desc("ICache total stall cycles")
145 .prereq(icacheStallCycles)
146 ;
147
148 dcacheStallCycles
149 .name(name() + ".dcache_stall_cycles")
150 .desc("DCache total stall cycles")
151 .prereq(dcacheStallCycles)
152 ;
153
154 icacheRetryCycles
155 .name(name() + ".icache_retry_cycles")
156 .desc("ICache total retry cycles")
157 .prereq(icacheRetryCycles)
158 ;
159
160 dcacheRetryCycles
161 .name(name() + ".dcache_retry_cycles")
162 .desc("DCache total retry cycles")
163 .prereq(dcacheRetryCycles)
164 ;
165
166 idleFraction = constant(1.0) - notIdleFraction;
167}
168
169void
170BaseSimpleCPU::resetStats()
171{
172 startNumInst = numInst;
173 // notIdleFraction = (_status != Idle);
174}
175
176void
177BaseSimpleCPU::serialize(ostream &os)
178{
179 BaseCPU::serialize(os);
180// SERIALIZE_SCALAR(inst);
181 nameOut(os, csprintf("%s.xc.0", name()));
182 thread->serialize(os);
183}
184
185void
186BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
187{
188 BaseCPU::unserialize(cp, section);
189// UNSERIALIZE_SCALAR(inst);
190 thread->unserialize(cp, csprintf("%s.xc.0", section));
191}
192
193void
194change_thread_state(int thread_number, int activate, int priority)
195{
196}
197
198Fault
199BaseSimpleCPU::copySrcTranslate(Addr src)
200{
201#if 0
202 static bool no_warn = true;
203 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
204 // Only support block sizes of 64 atm.
205 assert(blk_size == 64);
206 int offset = src & (blk_size - 1);
207
208 // Make sure block doesn't span page
209 if (no_warn &&
210 (src & PageMask) != ((src + blk_size) & PageMask) &&
211 (src >> 40) != 0xfffffc) {
212 warn("Copied block source spans pages %x.", src);
213 no_warn = false;
214 }
215
216 memReq->reset(src & ~(blk_size - 1), blk_size);
217
218 // translate to physical address
219 Fault fault = thread->translateDataReadReq(req);
220
221 if (fault == NoFault) {
222 thread->copySrcAddr = src;
223 thread->copySrcPhysAddr = memReq->paddr + offset;
224 } else {
225 assert(!fault->isAlignmentFault());
226
227 thread->copySrcAddr = 0;
228 thread->copySrcPhysAddr = 0;
229 }
230 return fault;
231#else
232 return NoFault;
233#endif
234}
235
236Fault
237BaseSimpleCPU::copy(Addr dest)
238{
239#if 0
240 static bool no_warn = true;
241 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
242 // Only support block sizes of 64 atm.
243 assert(blk_size == 64);
244 uint8_t data[blk_size];
245 //assert(thread->copySrcAddr);
246 int offset = dest & (blk_size - 1);
247
248 // Make sure block doesn't span page
249 if (no_warn &&
250 (dest & PageMask) != ((dest + blk_size) & PageMask) &&
251 (dest >> 40) != 0xfffffc) {
252 no_warn = false;
253 warn("Copied block destination spans pages %x. ", dest);
254 }
255
256 memReq->reset(dest & ~(blk_size -1), blk_size);
257 // translate to physical address
258 Fault fault = thread->translateDataWriteReq(req);
259
260 if (fault == NoFault) {
261 Addr dest_addr = memReq->paddr + offset;
262 // Need to read straight from memory since we have more than 8 bytes.
263 memReq->paddr = thread->copySrcPhysAddr;
264 thread->mem->read(memReq, data);
265 memReq->paddr = dest_addr;
266 thread->mem->write(memReq, data);
267 if (dcacheInterface) {
268 memReq->cmd = Copy;
269 memReq->completionEvent = NULL;
270 memReq->paddr = thread->copySrcPhysAddr;
271 memReq->dest = dest_addr;
272 memReq->size = 64;
273 memReq->time = curTick;
274 memReq->flags &= ~INST_READ;
275 dcacheInterface->access(memReq);
276 }
277 }
278 else
279 assert(!fault->isAlignmentFault());
280
281 return fault;
282#else
283 panic("copy not implemented");
284 return NoFault;
285#endif
286}
287
288#if FULL_SYSTEM
289Addr
290BaseSimpleCPU::dbg_vtophys(Addr addr)
291{
292 return vtophys(tc, addr);
293}
294#endif // FULL_SYSTEM
295
296#if FULL_SYSTEM
297void
298BaseSimpleCPU::post_interrupt(int int_num, int index)
299{
300 BaseCPU::post_interrupt(int_num, index);
301
302 if (thread->status() == ThreadContext::Suspended) {
303 DPRINTF(IPI,"Suspended Processor awoke\n");
304 thread->activate();
305 }
306}
307#endif // FULL_SYSTEM
308
309void
310BaseSimpleCPU::checkForInterrupts()
311{
312#if FULL_SYSTEM
313 if (checkInterrupts && check_interrupts() && !thread->inPalMode()) {
314 int ipl = 0;
315 int summary = 0;
316 checkInterrupts = false;
317
318 if (thread->readMiscReg(IPR_SIRR)) {
319 for (int i = INTLEVEL_SOFTWARE_MIN;
320 i < INTLEVEL_SOFTWARE_MAX; i++) {
321 if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
322 // See table 4-19 of 21164 hardware reference
323 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
324 summary |= (ULL(1) << i);
325 }
326 }
327 }
328
329 uint64_t interrupts = thread->cpu->intr_status();
330 for (int i = INTLEVEL_EXTERNAL_MIN;
331 i < INTLEVEL_EXTERNAL_MAX; i++) {
332 if (interrupts & (ULL(1) << i)) {
333 // See table 4-19 of 21164 hardware reference
334 ipl = i;
335 summary |= (ULL(1) << i);
336 }
337 }
338
339 if (thread->readMiscReg(IPR_ASTRR))
340 panic("asynchronous traps not implemented\n");
341
342 if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
343 thread->setMiscReg(IPR_ISR, summary);
344 thread->setMiscReg(IPR_INTID, ipl);
345
346 Fault(new InterruptFault)->invoke(tc);
347
348 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
349 thread->readMiscReg(IPR_IPLR), ipl, summary);
350 }
351 }
352#endif
353}
354
355
356Fault
357BaseSimpleCPU::setupFetchRequest(Request *req)
358{
359 // set up memory request for instruction fetch
360#if THE_ISA == ALPHA_ISA
361 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
362 thread->readNextPC());
363#else
364 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
365 thread->readNextPC(),thread->readNextNPC());
366#endif
367
368 req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
369 (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0,
370 thread->readPC());
371
372 Fault fault = thread->translateInstReq(req);
373
374 return fault;
375}
376
377
378void
379BaseSimpleCPU::preExecute()
380{
381 // maintain $r0 semantics
382 thread->setIntReg(ZeroReg, 0);
383#if THE_ISA == ALPHA_ISA
384 thread->setFloatReg(ZeroReg, 0.0);
385#endif // ALPHA_ISA
386
387 // keep an instruction count
388 numInst++;
389 numInsts++;
390
391 thread->funcExeInst++;
392
393 // check for instruction-count-based events
394 comInstEventQueue[0]->serviceEvents(numInst);
395
396 // decode the instruction
397 inst = gtoh(inst);
398 curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC()));
399
400 traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst,
401 thread->readPC());
402
403 DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
404 curStaticInst->getName(), curStaticInst->getOpcode(),
405 curStaticInst->machInst);
406
407#if FULL_SYSTEM
408 thread->setInst(inst);
409#endif // FULL_SYSTEM
410}
411
412void
413BaseSimpleCPU::postExecute()
414{
415#if FULL_SYSTEM
416 if (thread->profile) {
417 bool usermode =
418 (thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
419 thread->profilePC = usermode ? 1 : thread->readPC();
420 ProfileNode *node = thread->profile->consume(tc, inst);
421 if (node)
422 thread->profileNode = node;
423 }
424#endif
425
426 if (curStaticInst->isMemRef()) {
427 numMemRefs++;
428 }
429
430 if (curStaticInst->isLoad()) {
431 ++numLoad;
432 comLoadEventQueue[0]->serviceEvents(numLoad);
433 }
434
435 traceFunctions(thread->readPC());
436
437 if (traceData) {
438 traceData->finalize();
439 }
440}
441
442
443void
444BaseSimpleCPU::advancePC(Fault fault)
445{
446 if (fault != NoFault) {
447 fault->invoke(tc);
448 }
449 else {
450 // go to the next instruction
451 thread->setPC(thread->readNextPC());
452#if THE_ISA == ALPHA_ISA
453 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
454#else
455 thread->setNextPC(thread->readNextNPC());
456 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
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