1/*
2 * Copyright (c) 2010-2012, 2015, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "cpu/simple/base.hh"
45
46#include "arch/kernel_stats.hh"
47#include "arch/stacktrace.hh"
48#include "arch/tlb.hh"
49#include "arch/utility.hh"
50#include "arch/vtophys.hh"
51#include "base/cp_annotate.hh"
52#include "base/cprintf.hh"
53#include "base/inifile.hh"
54#include "base/loader/symtab.hh"
| 1/*
2 * Copyright (c) 2010-2012, 2015, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "cpu/simple/base.hh"
45
46#include "arch/kernel_stats.hh"
47#include "arch/stacktrace.hh"
48#include "arch/tlb.hh"
49#include "arch/utility.hh"
50#include "arch/vtophys.hh"
51#include "base/cp_annotate.hh"
52#include "base/cprintf.hh"
53#include "base/inifile.hh"
54#include "base/loader/symtab.hh"
|
56#include "base/pollevent.hh"
57#include "base/trace.hh"
58#include "base/types.hh"
59#include "config/the_isa.hh"
60#include "cpu/base.hh"
61#include "cpu/checker/cpu.hh"
62#include "cpu/checker/thread_context.hh"
63#include "cpu/exetrace.hh"
64#include "cpu/pred/bpred_unit.hh"
65#include "cpu/profile.hh"
66#include "cpu/simple/exec_context.hh"
67#include "cpu/simple_thread.hh"
68#include "cpu/smt.hh"
69#include "cpu/static_inst.hh"
70#include "cpu/thread_context.hh"
71#include "debug/Decode.hh"
72#include "debug/Fetch.hh"
73#include "debug/Quiesce.hh"
74#include "mem/mem_object.hh"
75#include "mem/packet.hh"
76#include "mem/request.hh"
77#include "params/BaseSimpleCPU.hh"
78#include "sim/byteswap.hh"
79#include "sim/debug.hh"
80#include "sim/faults.hh"
81#include "sim/full_system.hh"
82#include "sim/sim_events.hh"
83#include "sim/sim_object.hh"
84#include "sim/stats.hh"
85#include "sim/system.hh"
86
87using namespace std;
88using namespace TheISA;
89
90BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
91 : BaseCPU(p),
92 curThread(0),
93 branchPred(p->branchPred),
94 traceData(NULL),
95 inst(),
96 _status(Idle)
97{
98 SimpleThread *thread;
99
100 for (unsigned i = 0; i < numThreads; i++) {
101 if (FullSystem) {
102 thread = new SimpleThread(this, i, p->system,
103 p->itb, p->dtb, p->isa[i]);
104 } else {
105 thread = new SimpleThread(this, i, p->system, p->workload[i],
106 p->itb, p->dtb, p->isa[i]);
107 }
108 threadInfo.push_back(new SimpleExecContext(this, thread));
109 ThreadContext *tc = thread->getTC();
110 threadContexts.push_back(tc);
111 }
112
113 if (p->checker) {
114 if (numThreads != 1)
115 fatal("Checker currently does not support SMT");
116
117 BaseCPU *temp_checker = p->checker;
118 checker = dynamic_cast<CheckerCPU *>(temp_checker);
119 checker->setSystem(p->system);
120 // Manipulate thread context
121 ThreadContext *cpu_tc = threadContexts[0];
122 threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
123 } else {
124 checker = NULL;
125 }
126}
127
128void
129BaseSimpleCPU::init()
130{
131 BaseCPU::init();
132
133 for (auto tc : threadContexts) {
134 // Initialise the ThreadContext's memory proxies
135 tc->initMemProxies(tc);
136
137 if (FullSystem && !params()->switched_out) {
138 // initialize CPU, including PC
139 TheISA::initCPU(tc, tc->contextId());
140 }
141 }
142}
143
144void
145BaseSimpleCPU::checkPcEventQueue()
146{
147 Addr oldpc, pc = threadInfo[curThread]->thread->instAddr();
148 do {
149 oldpc = pc;
150 system->pcEventQueue.service(threadContexts[curThread]);
151 pc = threadInfo[curThread]->thread->instAddr();
152 } while (oldpc != pc);
153}
154
155void
156BaseSimpleCPU::swapActiveThread()
157{
158 if (numThreads > 1) {
159 if ((!curStaticInst || !curStaticInst->isDelayedCommit()) &&
160 !threadInfo[curThread]->stayAtPC) {
161 // Swap active threads
162 if (!activeThreads.empty()) {
163 curThread = activeThreads.front();
164 activeThreads.pop_front();
165 activeThreads.push_back(curThread);
166 }
167 }
168 }
169}
170
171void
172BaseSimpleCPU::countInst()
173{
174 SimpleExecContext& t_info = *threadInfo[curThread];
175
176 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
177 t_info.numInst++;
178 t_info.numInsts++;
179 }
180 t_info.numOp++;
181 t_info.numOps++;
182
183 system->totalNumInsts++;
184 t_info.thread->funcExeInst++;
185}
186
187Counter
188BaseSimpleCPU::totalInsts() const
189{
190 Counter total_inst = 0;
191 for (auto& t_info : threadInfo) {
192 total_inst += t_info->numInst;
193 }
194
195 return total_inst;
196}
197
198Counter
199BaseSimpleCPU::totalOps() const
200{
201 Counter total_op = 0;
202 for (auto& t_info : threadInfo) {
203 total_op += t_info->numOp;
204 }
205
206 return total_op;
207}
208
209BaseSimpleCPU::~BaseSimpleCPU()
210{
211}
212
213void
214BaseSimpleCPU::haltContext(ThreadID thread_num)
215{
216 // for now, these are equivalent
217 suspendContext(thread_num);
218 updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
219}
220
221
222void
223BaseSimpleCPU::regStats()
224{
225 using namespace Stats;
226
227 BaseCPU::regStats();
228
229 for (ThreadID tid = 0; tid < numThreads; tid++) {
230 SimpleExecContext& t_info = *threadInfo[tid];
231
232 std::string thread_str = name();
233 if (numThreads > 1)
234 thread_str += ".thread" + std::to_string(tid);
235
236 t_info.numInsts
237 .name(thread_str + ".committedInsts")
238 .desc("Number of instructions committed")
239 ;
240
241 t_info.numOps
242 .name(thread_str + ".committedOps")
243 .desc("Number of ops (including micro ops) committed")
244 ;
245
246 t_info.numIntAluAccesses
247 .name(thread_str + ".num_int_alu_accesses")
248 .desc("Number of integer alu accesses")
249 ;
250
251 t_info.numFpAluAccesses
252 .name(thread_str + ".num_fp_alu_accesses")
253 .desc("Number of float alu accesses")
254 ;
255
256 t_info.numVecAluAccesses
257 .name(thread_str + ".num_vec_alu_accesses")
258 .desc("Number of vector alu accesses")
259 ;
260
261 t_info.numCallsReturns
262 .name(thread_str + ".num_func_calls")
263 .desc("number of times a function call or return occured")
264 ;
265
266 t_info.numCondCtrlInsts
267 .name(thread_str + ".num_conditional_control_insts")
268 .desc("number of instructions that are conditional controls")
269 ;
270
271 t_info.numIntInsts
272 .name(thread_str + ".num_int_insts")
273 .desc("number of integer instructions")
274 ;
275
276 t_info.numFpInsts
277 .name(thread_str + ".num_fp_insts")
278 .desc("number of float instructions")
279 ;
280
281 t_info.numVecInsts
282 .name(thread_str + ".num_vec_insts")
283 .desc("number of vector instructions")
284 ;
285
286 t_info.numIntRegReads
287 .name(thread_str + ".num_int_register_reads")
288 .desc("number of times the integer registers were read")
289 ;
290
291 t_info.numIntRegWrites
292 .name(thread_str + ".num_int_register_writes")
293 .desc("number of times the integer registers were written")
294 ;
295
296 t_info.numFpRegReads
297 .name(thread_str + ".num_fp_register_reads")
298 .desc("number of times the floating registers were read")
299 ;
300
301 t_info.numFpRegWrites
302 .name(thread_str + ".num_fp_register_writes")
303 .desc("number of times the floating registers were written")
304 ;
305
306 t_info.numVecRegReads
307 .name(thread_str + ".num_vec_register_reads")
308 .desc("number of times the vector registers were read")
309 ;
310
311 t_info.numVecRegWrites
312 .name(thread_str + ".num_vec_register_writes")
313 .desc("number of times the vector registers were written")
314 ;
315
316 t_info.numCCRegReads
317 .name(thread_str + ".num_cc_register_reads")
318 .desc("number of times the CC registers were read")
319 .flags(nozero)
320 ;
321
322 t_info.numCCRegWrites
323 .name(thread_str + ".num_cc_register_writes")
324 .desc("number of times the CC registers were written")
325 .flags(nozero)
326 ;
327
328 t_info.numMemRefs
329 .name(thread_str + ".num_mem_refs")
330 .desc("number of memory refs")
331 ;
332
333 t_info.numStoreInsts
334 .name(thread_str + ".num_store_insts")
335 .desc("Number of store instructions")
336 ;
337
338 t_info.numLoadInsts
339 .name(thread_str + ".num_load_insts")
340 .desc("Number of load instructions")
341 ;
342
343 t_info.notIdleFraction
344 .name(thread_str + ".not_idle_fraction")
345 .desc("Percentage of non-idle cycles")
346 ;
347
348 t_info.idleFraction
349 .name(thread_str + ".idle_fraction")
350 .desc("Percentage of idle cycles")
351 ;
352
353 t_info.numBusyCycles
354 .name(thread_str + ".num_busy_cycles")
355 .desc("Number of busy cycles")
356 ;
357
358 t_info.numIdleCycles
359 .name(thread_str + ".num_idle_cycles")
360 .desc("Number of idle cycles")
361 ;
362
363 t_info.icacheStallCycles
364 .name(thread_str + ".icache_stall_cycles")
365 .desc("ICache total stall cycles")
366 .prereq(t_info.icacheStallCycles)
367 ;
368
369 t_info.dcacheStallCycles
370 .name(thread_str + ".dcache_stall_cycles")
371 .desc("DCache total stall cycles")
372 .prereq(t_info.dcacheStallCycles)
373 ;
374
375 t_info.statExecutedInstType
376 .init(Enums::Num_OpClass)
377 .name(thread_str + ".op_class")
378 .desc("Class of executed instruction")
379 .flags(total | pdf | dist)
380 ;
381
382 for (unsigned i = 0; i < Num_OpClasses; ++i) {
383 t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
384 }
385
386 t_info.idleFraction = constant(1.0) - t_info.notIdleFraction;
387 t_info.numIdleCycles = t_info.idleFraction * numCycles;
388 t_info.numBusyCycles = t_info.notIdleFraction * numCycles;
389
390 t_info.numBranches
391 .name(thread_str + ".Branches")
392 .desc("Number of branches fetched")
393 .prereq(t_info.numBranches);
394
395 t_info.numPredictedBranches
396 .name(thread_str + ".predictedBranches")
397 .desc("Number of branches predicted as taken")
398 .prereq(t_info.numPredictedBranches);
399
400 t_info.numBranchMispred
401 .name(thread_str + ".BranchMispred")
402 .desc("Number of branch mispredictions")
403 .prereq(t_info.numBranchMispred);
404 }
405}
406
407void
408BaseSimpleCPU::resetStats()
409{
410 for (auto &thread_info : threadInfo) {
411 thread_info->notIdleFraction = (_status != Idle);
412 }
413}
414
415void
416BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
417{
418 assert(_status == Idle || _status == Running);
419
420 threadInfo[tid]->thread->serialize(cp);
421}
422
423void
424BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid)
425{
426 threadInfo[tid]->thread->unserialize(cp);
427}
428
429void
430change_thread_state(ThreadID tid, int activate, int priority)
431{
432}
433
434Addr
435BaseSimpleCPU::dbg_vtophys(Addr addr)
436{
437 return vtophys(threadContexts[curThread], addr);
438}
439
440void
441BaseSimpleCPU::wakeup(ThreadID tid)
442{
443 getCpuAddrMonitor(tid)->gotWakeup = true;
444
445 if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
446 DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
447 threadInfo[tid]->thread->activate();
448 }
449}
450
451void
452BaseSimpleCPU::checkForInterrupts()
453{
454 SimpleExecContext&t_info = *threadInfo[curThread];
455 SimpleThread* thread = t_info.thread;
456 ThreadContext* tc = thread->getTC();
457
458 if (checkInterrupts(tc)) {
459 Fault interrupt = interrupts[curThread]->getInterrupt(tc);
460
461 if (interrupt != NoFault) {
462 t_info.fetchOffset = 0;
463 interrupts[curThread]->updateIntrInfo(tc);
464 interrupt->invoke(tc);
465 thread->decoder.reset();
466 }
467 }
468}
469
470
471void
472BaseSimpleCPU::setupFetchRequest(Request *req)
473{
474 SimpleExecContext &t_info = *threadInfo[curThread];
475 SimpleThread* thread = t_info.thread;
476
477 Addr instAddr = thread->instAddr();
478
479 // set up memory request for instruction fetch
480 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
481
482 Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
483 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
484 instAddr);
485}
486
487
488void
489BaseSimpleCPU::preExecute()
490{
491 SimpleExecContext &t_info = *threadInfo[curThread];
492 SimpleThread* thread = t_info.thread;
493
494 // maintain $r0 semantics
495 thread->setIntReg(ZeroReg, 0);
496#if THE_ISA == ALPHA_ISA
497 thread->setFloatReg(ZeroReg, 0.0);
498#endif // ALPHA_ISA
499
500 // check for instruction-count-based events
501 comInstEventQueue[curThread]->serviceEvents(t_info.numInst);
502 system->instEventQueue.serviceEvents(system->totalNumInsts);
503
504 // decode the instruction
505 inst = gtoh(inst);
506
507 TheISA::PCState pcState = thread->pcState();
508
509 if (isRomMicroPC(pcState.microPC())) {
510 t_info.stayAtPC = false;
511 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
512 curMacroStaticInst);
513 } else if (!curMacroStaticInst) {
514 //We're not in the middle of a macro instruction
515 StaticInstPtr instPtr = NULL;
516
517 TheISA::Decoder *decoder = &(thread->decoder);
518
519 //Predecode, ie bundle up an ExtMachInst
520 //If more fetch data is needed, pass it in.
521 Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset;
522 //if (decoder->needMoreBytes())
523 decoder->moreBytes(pcState, fetchPC, inst);
524 //else
525 // decoder->process();
526
527 //Decode an instruction if one is ready. Otherwise, we'll have to
528 //fetch beyond the MachInst at the current pc.
529 instPtr = decoder->decode(pcState);
530 if (instPtr) {
531 t_info.stayAtPC = false;
532 thread->pcState(pcState);
533 } else {
534 t_info.stayAtPC = true;
535 t_info.fetchOffset += sizeof(MachInst);
536 }
537
538 //If we decoded an instruction and it's microcoded, start pulling
539 //out micro ops
540 if (instPtr && instPtr->isMacroop()) {
541 curMacroStaticInst = instPtr;
542 curStaticInst =
543 curMacroStaticInst->fetchMicroop(pcState.microPC());
544 } else {
545 curStaticInst = instPtr;
546 }
547 } else {
548 //Read the next micro op from the macro op
549 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
550 }
551
552 //If we decoded an instruction this "tick", record information about it.
553 if (curStaticInst) {
554#if TRACING_ON
555 traceData = tracer->getInstRecord(curTick(), thread->getTC(),
556 curStaticInst, thread->pcState(), curMacroStaticInst);
557
558 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
559 curStaticInst->getName(), curStaticInst->machInst);
560#endif // TRACING_ON
561 }
562
563 if (branchPred && curStaticInst &&
564 curStaticInst->isControl()) {
565 // Use a fake sequence number since we only have one
566 // instruction in flight at the same time.
567 const InstSeqNum cur_sn(0);
568 t_info.predPC = thread->pcState();
569 const bool predict_taken(
570 branchPred->predict(curStaticInst, cur_sn, t_info.predPC,
571 curThread));
572
573 if (predict_taken)
574 ++t_info.numPredictedBranches;
575 }
576}
577
578void
579BaseSimpleCPU::postExecute()
580{
581 SimpleExecContext &t_info = *threadInfo[curThread];
582 SimpleThread* thread = t_info.thread;
583
584 assert(curStaticInst);
585
586 TheISA::PCState pc = threadContexts[curThread]->pcState();
587 Addr instAddr = pc.instAddr();
588 if (FullSystem && thread->profile) {
589 bool usermode = TheISA::inUserMode(threadContexts[curThread]);
590 thread->profilePC = usermode ? 1 : instAddr;
591 ProfileNode *node = thread->profile->consume(threadContexts[curThread],
592 curStaticInst);
593 if (node)
594 thread->profileNode = node;
595 }
596
597 if (curStaticInst->isMemRef()) {
598 t_info.numMemRefs++;
599 }
600
601 if (curStaticInst->isLoad()) {
602 ++t_info.numLoad;
603 comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad);
604 }
605
606 if (CPA::available()) {
607 CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr());
608 }
609
610 if (curStaticInst->isControl()) {
611 ++t_info.numBranches;
612 }
613
614 /* Power model statistics */
615 //integer alu accesses
616 if (curStaticInst->isInteger()){
617 t_info.numIntAluAccesses++;
618 t_info.numIntInsts++;
619 }
620
621 //float alu accesses
622 if (curStaticInst->isFloating()){
623 t_info.numFpAluAccesses++;
624 t_info.numFpInsts++;
625 }
626
627 //vector alu accesses
628 if (curStaticInst->isVector()){
629 t_info.numVecAluAccesses++;
630 t_info.numVecInsts++;
631 }
632
633 //number of function calls/returns to get window accesses
634 if (curStaticInst->isCall() || curStaticInst->isReturn()){
635 t_info.numCallsReturns++;
636 }
637
638 //the number of branch predictions that will be made
639 if (curStaticInst->isCondCtrl()){
640 t_info.numCondCtrlInsts++;
641 }
642
643 //result bus acceses
644 if (curStaticInst->isLoad()){
645 t_info.numLoadInsts++;
646 }
647
648 if (curStaticInst->isStore()){
649 t_info.numStoreInsts++;
650 }
651 /* End power model statistics */
652
653 t_info.statExecutedInstType[curStaticInst->opClass()]++;
654
655 if (FullSystem)
656 traceFunctions(instAddr);
657
658 if (traceData) {
659 traceData->dump();
660 delete traceData;
661 traceData = NULL;
662 }
663
664 // Call CPU instruction commit probes
665 probeInstCommit(curStaticInst);
666}
667
668void
669BaseSimpleCPU::advancePC(const Fault &fault)
670{
671 SimpleExecContext &t_info = *threadInfo[curThread];
672 SimpleThread* thread = t_info.thread;
673
674 const bool branching(thread->pcState().branching());
675
676 //Since we're moving to a new pc, zero out the offset
677 t_info.fetchOffset = 0;
678 if (fault != NoFault) {
679 curMacroStaticInst = StaticInst::nullStaticInstPtr;
680 fault->invoke(threadContexts[curThread], curStaticInst);
681 thread->decoder.reset();
682 } else {
683 if (curStaticInst) {
684 if (curStaticInst->isLastMicroop())
685 curMacroStaticInst = StaticInst::nullStaticInstPtr;
686 TheISA::PCState pcState = thread->pcState();
687 TheISA::advancePC(pcState, curStaticInst);
688 thread->pcState(pcState);
689 }
690 }
691
692 if (branchPred && curStaticInst && curStaticInst->isControl()) {
693 // Use a fake sequence number since we only have one
694 // instruction in flight at the same time.
695 const InstSeqNum cur_sn(0);
696
697 if (t_info.predPC == thread->pcState()) {
698 // Correctly predicted branch
699 branchPred->update(cur_sn, curThread);
700 } else {
701 // Mis-predicted branch
702 branchPred->squash(cur_sn, thread->pcState(), branching, curThread);
703 ++t_info.numBranchMispred;
704 }
705 }
706}
707
708void
709BaseSimpleCPU::startup()
710{
711 BaseCPU::startup();
712 for (auto& t_info : threadInfo)
713 t_info->thread->startup();
714}
| 56#include "base/pollevent.hh"
57#include "base/trace.hh"
58#include "base/types.hh"
59#include "config/the_isa.hh"
60#include "cpu/base.hh"
61#include "cpu/checker/cpu.hh"
62#include "cpu/checker/thread_context.hh"
63#include "cpu/exetrace.hh"
64#include "cpu/pred/bpred_unit.hh"
65#include "cpu/profile.hh"
66#include "cpu/simple/exec_context.hh"
67#include "cpu/simple_thread.hh"
68#include "cpu/smt.hh"
69#include "cpu/static_inst.hh"
70#include "cpu/thread_context.hh"
71#include "debug/Decode.hh"
72#include "debug/Fetch.hh"
73#include "debug/Quiesce.hh"
74#include "mem/mem_object.hh"
75#include "mem/packet.hh"
76#include "mem/request.hh"
77#include "params/BaseSimpleCPU.hh"
78#include "sim/byteswap.hh"
79#include "sim/debug.hh"
80#include "sim/faults.hh"
81#include "sim/full_system.hh"
82#include "sim/sim_events.hh"
83#include "sim/sim_object.hh"
84#include "sim/stats.hh"
85#include "sim/system.hh"
86
87using namespace std;
88using namespace TheISA;
89
90BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
91 : BaseCPU(p),
92 curThread(0),
93 branchPred(p->branchPred),
94 traceData(NULL),
95 inst(),
96 _status(Idle)
97{
98 SimpleThread *thread;
99
100 for (unsigned i = 0; i < numThreads; i++) {
101 if (FullSystem) {
102 thread = new SimpleThread(this, i, p->system,
103 p->itb, p->dtb, p->isa[i]);
104 } else {
105 thread = new SimpleThread(this, i, p->system, p->workload[i],
106 p->itb, p->dtb, p->isa[i]);
107 }
108 threadInfo.push_back(new SimpleExecContext(this, thread));
109 ThreadContext *tc = thread->getTC();
110 threadContexts.push_back(tc);
111 }
112
113 if (p->checker) {
114 if (numThreads != 1)
115 fatal("Checker currently does not support SMT");
116
117 BaseCPU *temp_checker = p->checker;
118 checker = dynamic_cast<CheckerCPU *>(temp_checker);
119 checker->setSystem(p->system);
120 // Manipulate thread context
121 ThreadContext *cpu_tc = threadContexts[0];
122 threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
123 } else {
124 checker = NULL;
125 }
126}
127
128void
129BaseSimpleCPU::init()
130{
131 BaseCPU::init();
132
133 for (auto tc : threadContexts) {
134 // Initialise the ThreadContext's memory proxies
135 tc->initMemProxies(tc);
136
137 if (FullSystem && !params()->switched_out) {
138 // initialize CPU, including PC
139 TheISA::initCPU(tc, tc->contextId());
140 }
141 }
142}
143
144void
145BaseSimpleCPU::checkPcEventQueue()
146{
147 Addr oldpc, pc = threadInfo[curThread]->thread->instAddr();
148 do {
149 oldpc = pc;
150 system->pcEventQueue.service(threadContexts[curThread]);
151 pc = threadInfo[curThread]->thread->instAddr();
152 } while (oldpc != pc);
153}
154
155void
156BaseSimpleCPU::swapActiveThread()
157{
158 if (numThreads > 1) {
159 if ((!curStaticInst || !curStaticInst->isDelayedCommit()) &&
160 !threadInfo[curThread]->stayAtPC) {
161 // Swap active threads
162 if (!activeThreads.empty()) {
163 curThread = activeThreads.front();
164 activeThreads.pop_front();
165 activeThreads.push_back(curThread);
166 }
167 }
168 }
169}
170
171void
172BaseSimpleCPU::countInst()
173{
174 SimpleExecContext& t_info = *threadInfo[curThread];
175
176 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
177 t_info.numInst++;
178 t_info.numInsts++;
179 }
180 t_info.numOp++;
181 t_info.numOps++;
182
183 system->totalNumInsts++;
184 t_info.thread->funcExeInst++;
185}
186
187Counter
188BaseSimpleCPU::totalInsts() const
189{
190 Counter total_inst = 0;
191 for (auto& t_info : threadInfo) {
192 total_inst += t_info->numInst;
193 }
194
195 return total_inst;
196}
197
198Counter
199BaseSimpleCPU::totalOps() const
200{
201 Counter total_op = 0;
202 for (auto& t_info : threadInfo) {
203 total_op += t_info->numOp;
204 }
205
206 return total_op;
207}
208
209BaseSimpleCPU::~BaseSimpleCPU()
210{
211}
212
213void
214BaseSimpleCPU::haltContext(ThreadID thread_num)
215{
216 // for now, these are equivalent
217 suspendContext(thread_num);
218 updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
219}
220
221
222void
223BaseSimpleCPU::regStats()
224{
225 using namespace Stats;
226
227 BaseCPU::regStats();
228
229 for (ThreadID tid = 0; tid < numThreads; tid++) {
230 SimpleExecContext& t_info = *threadInfo[tid];
231
232 std::string thread_str = name();
233 if (numThreads > 1)
234 thread_str += ".thread" + std::to_string(tid);
235
236 t_info.numInsts
237 .name(thread_str + ".committedInsts")
238 .desc("Number of instructions committed")
239 ;
240
241 t_info.numOps
242 .name(thread_str + ".committedOps")
243 .desc("Number of ops (including micro ops) committed")
244 ;
245
246 t_info.numIntAluAccesses
247 .name(thread_str + ".num_int_alu_accesses")
248 .desc("Number of integer alu accesses")
249 ;
250
251 t_info.numFpAluAccesses
252 .name(thread_str + ".num_fp_alu_accesses")
253 .desc("Number of float alu accesses")
254 ;
255
256 t_info.numVecAluAccesses
257 .name(thread_str + ".num_vec_alu_accesses")
258 .desc("Number of vector alu accesses")
259 ;
260
261 t_info.numCallsReturns
262 .name(thread_str + ".num_func_calls")
263 .desc("number of times a function call or return occured")
264 ;
265
266 t_info.numCondCtrlInsts
267 .name(thread_str + ".num_conditional_control_insts")
268 .desc("number of instructions that are conditional controls")
269 ;
270
271 t_info.numIntInsts
272 .name(thread_str + ".num_int_insts")
273 .desc("number of integer instructions")
274 ;
275
276 t_info.numFpInsts
277 .name(thread_str + ".num_fp_insts")
278 .desc("number of float instructions")
279 ;
280
281 t_info.numVecInsts
282 .name(thread_str + ".num_vec_insts")
283 .desc("number of vector instructions")
284 ;
285
286 t_info.numIntRegReads
287 .name(thread_str + ".num_int_register_reads")
288 .desc("number of times the integer registers were read")
289 ;
290
291 t_info.numIntRegWrites
292 .name(thread_str + ".num_int_register_writes")
293 .desc("number of times the integer registers were written")
294 ;
295
296 t_info.numFpRegReads
297 .name(thread_str + ".num_fp_register_reads")
298 .desc("number of times the floating registers were read")
299 ;
300
301 t_info.numFpRegWrites
302 .name(thread_str + ".num_fp_register_writes")
303 .desc("number of times the floating registers were written")
304 ;
305
306 t_info.numVecRegReads
307 .name(thread_str + ".num_vec_register_reads")
308 .desc("number of times the vector registers were read")
309 ;
310
311 t_info.numVecRegWrites
312 .name(thread_str + ".num_vec_register_writes")
313 .desc("number of times the vector registers were written")
314 ;
315
316 t_info.numCCRegReads
317 .name(thread_str + ".num_cc_register_reads")
318 .desc("number of times the CC registers were read")
319 .flags(nozero)
320 ;
321
322 t_info.numCCRegWrites
323 .name(thread_str + ".num_cc_register_writes")
324 .desc("number of times the CC registers were written")
325 .flags(nozero)
326 ;
327
328 t_info.numMemRefs
329 .name(thread_str + ".num_mem_refs")
330 .desc("number of memory refs")
331 ;
332
333 t_info.numStoreInsts
334 .name(thread_str + ".num_store_insts")
335 .desc("Number of store instructions")
336 ;
337
338 t_info.numLoadInsts
339 .name(thread_str + ".num_load_insts")
340 .desc("Number of load instructions")
341 ;
342
343 t_info.notIdleFraction
344 .name(thread_str + ".not_idle_fraction")
345 .desc("Percentage of non-idle cycles")
346 ;
347
348 t_info.idleFraction
349 .name(thread_str + ".idle_fraction")
350 .desc("Percentage of idle cycles")
351 ;
352
353 t_info.numBusyCycles
354 .name(thread_str + ".num_busy_cycles")
355 .desc("Number of busy cycles")
356 ;
357
358 t_info.numIdleCycles
359 .name(thread_str + ".num_idle_cycles")
360 .desc("Number of idle cycles")
361 ;
362
363 t_info.icacheStallCycles
364 .name(thread_str + ".icache_stall_cycles")
365 .desc("ICache total stall cycles")
366 .prereq(t_info.icacheStallCycles)
367 ;
368
369 t_info.dcacheStallCycles
370 .name(thread_str + ".dcache_stall_cycles")
371 .desc("DCache total stall cycles")
372 .prereq(t_info.dcacheStallCycles)
373 ;
374
375 t_info.statExecutedInstType
376 .init(Enums::Num_OpClass)
377 .name(thread_str + ".op_class")
378 .desc("Class of executed instruction")
379 .flags(total | pdf | dist)
380 ;
381
382 for (unsigned i = 0; i < Num_OpClasses; ++i) {
383 t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
384 }
385
386 t_info.idleFraction = constant(1.0) - t_info.notIdleFraction;
387 t_info.numIdleCycles = t_info.idleFraction * numCycles;
388 t_info.numBusyCycles = t_info.notIdleFraction * numCycles;
389
390 t_info.numBranches
391 .name(thread_str + ".Branches")
392 .desc("Number of branches fetched")
393 .prereq(t_info.numBranches);
394
395 t_info.numPredictedBranches
396 .name(thread_str + ".predictedBranches")
397 .desc("Number of branches predicted as taken")
398 .prereq(t_info.numPredictedBranches);
399
400 t_info.numBranchMispred
401 .name(thread_str + ".BranchMispred")
402 .desc("Number of branch mispredictions")
403 .prereq(t_info.numBranchMispred);
404 }
405}
406
407void
408BaseSimpleCPU::resetStats()
409{
410 for (auto &thread_info : threadInfo) {
411 thread_info->notIdleFraction = (_status != Idle);
412 }
413}
414
415void
416BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
417{
418 assert(_status == Idle || _status == Running);
419
420 threadInfo[tid]->thread->serialize(cp);
421}
422
423void
424BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid)
425{
426 threadInfo[tid]->thread->unserialize(cp);
427}
428
429void
430change_thread_state(ThreadID tid, int activate, int priority)
431{
432}
433
434Addr
435BaseSimpleCPU::dbg_vtophys(Addr addr)
436{
437 return vtophys(threadContexts[curThread], addr);
438}
439
440void
441BaseSimpleCPU::wakeup(ThreadID tid)
442{
443 getCpuAddrMonitor(tid)->gotWakeup = true;
444
445 if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
446 DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
447 threadInfo[tid]->thread->activate();
448 }
449}
450
451void
452BaseSimpleCPU::checkForInterrupts()
453{
454 SimpleExecContext&t_info = *threadInfo[curThread];
455 SimpleThread* thread = t_info.thread;
456 ThreadContext* tc = thread->getTC();
457
458 if (checkInterrupts(tc)) {
459 Fault interrupt = interrupts[curThread]->getInterrupt(tc);
460
461 if (interrupt != NoFault) {
462 t_info.fetchOffset = 0;
463 interrupts[curThread]->updateIntrInfo(tc);
464 interrupt->invoke(tc);
465 thread->decoder.reset();
466 }
467 }
468}
469
470
471void
472BaseSimpleCPU::setupFetchRequest(Request *req)
473{
474 SimpleExecContext &t_info = *threadInfo[curThread];
475 SimpleThread* thread = t_info.thread;
476
477 Addr instAddr = thread->instAddr();
478
479 // set up memory request for instruction fetch
480 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
481
482 Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
483 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
484 instAddr);
485}
486
487
488void
489BaseSimpleCPU::preExecute()
490{
491 SimpleExecContext &t_info = *threadInfo[curThread];
492 SimpleThread* thread = t_info.thread;
493
494 // maintain $r0 semantics
495 thread->setIntReg(ZeroReg, 0);
496#if THE_ISA == ALPHA_ISA
497 thread->setFloatReg(ZeroReg, 0.0);
498#endif // ALPHA_ISA
499
500 // check for instruction-count-based events
501 comInstEventQueue[curThread]->serviceEvents(t_info.numInst);
502 system->instEventQueue.serviceEvents(system->totalNumInsts);
503
504 // decode the instruction
505 inst = gtoh(inst);
506
507 TheISA::PCState pcState = thread->pcState();
508
509 if (isRomMicroPC(pcState.microPC())) {
510 t_info.stayAtPC = false;
511 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
512 curMacroStaticInst);
513 } else if (!curMacroStaticInst) {
514 //We're not in the middle of a macro instruction
515 StaticInstPtr instPtr = NULL;
516
517 TheISA::Decoder *decoder = &(thread->decoder);
518
519 //Predecode, ie bundle up an ExtMachInst
520 //If more fetch data is needed, pass it in.
521 Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset;
522 //if (decoder->needMoreBytes())
523 decoder->moreBytes(pcState, fetchPC, inst);
524 //else
525 // decoder->process();
526
527 //Decode an instruction if one is ready. Otherwise, we'll have to
528 //fetch beyond the MachInst at the current pc.
529 instPtr = decoder->decode(pcState);
530 if (instPtr) {
531 t_info.stayAtPC = false;
532 thread->pcState(pcState);
533 } else {
534 t_info.stayAtPC = true;
535 t_info.fetchOffset += sizeof(MachInst);
536 }
537
538 //If we decoded an instruction and it's microcoded, start pulling
539 //out micro ops
540 if (instPtr && instPtr->isMacroop()) {
541 curMacroStaticInst = instPtr;
542 curStaticInst =
543 curMacroStaticInst->fetchMicroop(pcState.microPC());
544 } else {
545 curStaticInst = instPtr;
546 }
547 } else {
548 //Read the next micro op from the macro op
549 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
550 }
551
552 //If we decoded an instruction this "tick", record information about it.
553 if (curStaticInst) {
554#if TRACING_ON
555 traceData = tracer->getInstRecord(curTick(), thread->getTC(),
556 curStaticInst, thread->pcState(), curMacroStaticInst);
557
558 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
559 curStaticInst->getName(), curStaticInst->machInst);
560#endif // TRACING_ON
561 }
562
563 if (branchPred && curStaticInst &&
564 curStaticInst->isControl()) {
565 // Use a fake sequence number since we only have one
566 // instruction in flight at the same time.
567 const InstSeqNum cur_sn(0);
568 t_info.predPC = thread->pcState();
569 const bool predict_taken(
570 branchPred->predict(curStaticInst, cur_sn, t_info.predPC,
571 curThread));
572
573 if (predict_taken)
574 ++t_info.numPredictedBranches;
575 }
576}
577
578void
579BaseSimpleCPU::postExecute()
580{
581 SimpleExecContext &t_info = *threadInfo[curThread];
582 SimpleThread* thread = t_info.thread;
583
584 assert(curStaticInst);
585
586 TheISA::PCState pc = threadContexts[curThread]->pcState();
587 Addr instAddr = pc.instAddr();
588 if (FullSystem && thread->profile) {
589 bool usermode = TheISA::inUserMode(threadContexts[curThread]);
590 thread->profilePC = usermode ? 1 : instAddr;
591 ProfileNode *node = thread->profile->consume(threadContexts[curThread],
592 curStaticInst);
593 if (node)
594 thread->profileNode = node;
595 }
596
597 if (curStaticInst->isMemRef()) {
598 t_info.numMemRefs++;
599 }
600
601 if (curStaticInst->isLoad()) {
602 ++t_info.numLoad;
603 comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad);
604 }
605
606 if (CPA::available()) {
607 CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr());
608 }
609
610 if (curStaticInst->isControl()) {
611 ++t_info.numBranches;
612 }
613
614 /* Power model statistics */
615 //integer alu accesses
616 if (curStaticInst->isInteger()){
617 t_info.numIntAluAccesses++;
618 t_info.numIntInsts++;
619 }
620
621 //float alu accesses
622 if (curStaticInst->isFloating()){
623 t_info.numFpAluAccesses++;
624 t_info.numFpInsts++;
625 }
626
627 //vector alu accesses
628 if (curStaticInst->isVector()){
629 t_info.numVecAluAccesses++;
630 t_info.numVecInsts++;
631 }
632
633 //number of function calls/returns to get window accesses
634 if (curStaticInst->isCall() || curStaticInst->isReturn()){
635 t_info.numCallsReturns++;
636 }
637
638 //the number of branch predictions that will be made
639 if (curStaticInst->isCondCtrl()){
640 t_info.numCondCtrlInsts++;
641 }
642
643 //result bus acceses
644 if (curStaticInst->isLoad()){
645 t_info.numLoadInsts++;
646 }
647
648 if (curStaticInst->isStore()){
649 t_info.numStoreInsts++;
650 }
651 /* End power model statistics */
652
653 t_info.statExecutedInstType[curStaticInst->opClass()]++;
654
655 if (FullSystem)
656 traceFunctions(instAddr);
657
658 if (traceData) {
659 traceData->dump();
660 delete traceData;
661 traceData = NULL;
662 }
663
664 // Call CPU instruction commit probes
665 probeInstCommit(curStaticInst);
666}
667
668void
669BaseSimpleCPU::advancePC(const Fault &fault)
670{
671 SimpleExecContext &t_info = *threadInfo[curThread];
672 SimpleThread* thread = t_info.thread;
673
674 const bool branching(thread->pcState().branching());
675
676 //Since we're moving to a new pc, zero out the offset
677 t_info.fetchOffset = 0;
678 if (fault != NoFault) {
679 curMacroStaticInst = StaticInst::nullStaticInstPtr;
680 fault->invoke(threadContexts[curThread], curStaticInst);
681 thread->decoder.reset();
682 } else {
683 if (curStaticInst) {
684 if (curStaticInst->isLastMicroop())
685 curMacroStaticInst = StaticInst::nullStaticInstPtr;
686 TheISA::PCState pcState = thread->pcState();
687 TheISA::advancePC(pcState, curStaticInst);
688 thread->pcState(pcState);
689 }
690 }
691
692 if (branchPred && curStaticInst && curStaticInst->isControl()) {
693 // Use a fake sequence number since we only have one
694 // instruction in flight at the same time.
695 const InstSeqNum cur_sn(0);
696
697 if (t_info.predPC == thread->pcState()) {
698 // Correctly predicted branch
699 branchPred->update(cur_sn, curThread);
700 } else {
701 // Mis-predicted branch
702 branchPred->squash(cur_sn, thread->pcState(), branching, curThread);
703 ++t_info.numBranchMispred;
704 }
705 }
706}
707
708void
709BaseSimpleCPU::startup()
710{
711 BaseCPU::startup();
712 for (auto& t_info : threadInfo)
713 t_info->thread->startup();
714}
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