1/*
2 * Copyright (c) 2010-2012, 2015, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "cpu/simple/base.hh"
45
46#include "arch/kernel_stats.hh"
47#include "arch/stacktrace.hh"
48#include "arch/utility.hh"
49#include "arch/vtophys.hh"
50#include "base/cp_annotate.hh"
51#include "base/cprintf.hh"
52#include "base/inifile.hh"
53#include "base/loader/symtab.hh"
54#include "base/logging.hh"
55#include "base/pollevent.hh"
56#include "base/trace.hh"
57#include "base/types.hh"
58#include "config/the_isa.hh"
59#include "cpu/base.hh"
60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/pred/bpred_unit.hh"
64#include "cpu/profile.hh"
65#include "cpu/simple/exec_context.hh"
66#include "cpu/simple_thread.hh"
67#include "cpu/smt.hh"
68#include "cpu/static_inst.hh"
69#include "cpu/thread_context.hh"
70#include "debug/Decode.hh"
71#include "debug/Fetch.hh"
72#include "debug/Quiesce.hh"
73#include "mem/packet.hh"
74#include "mem/request.hh"
75#include "params/BaseSimpleCPU.hh"
76#include "sim/byteswap.hh"
77#include "sim/debug.hh"
78#include "sim/faults.hh"
79#include "sim/full_system.hh"
80#include "sim/sim_events.hh"
81#include "sim/sim_object.hh"
82#include "sim/stats.hh"
83#include "sim/system.hh"
84
85using namespace std;
86using namespace TheISA;
87
88BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
89 : BaseCPU(p),
90 curThread(0),
91 branchPred(p->branchPred),
92 traceData(NULL),
93 inst(),
94 _status(Idle)
95{
96 SimpleThread *thread;
97
98 for (unsigned i = 0; i < numThreads; i++) {
99 if (FullSystem) {
100 thread = new SimpleThread(this, i, p->system,
101 p->itb, p->dtb, p->isa[i]);
102 } else {
103 thread = new SimpleThread(this, i, p->system, p->workload[i],
104 p->itb, p->dtb, p->isa[i]);
105 }
106 threadInfo.push_back(new SimpleExecContext(this, thread));
107 ThreadContext *tc = thread->getTC();
108 threadContexts.push_back(tc);
109 }
110
111 if (p->checker) {
112 if (numThreads != 1)
113 fatal("Checker currently does not support SMT");
114
115 BaseCPU *temp_checker = p->checker;
116 checker = dynamic_cast<CheckerCPU *>(temp_checker);
117 checker->setSystem(p->system);
118 // Manipulate thread context
119 ThreadContext *cpu_tc = threadContexts[0];
120 threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
121 } else {
122 checker = NULL;
123 }
124}
125
126void
127BaseSimpleCPU::init()
128{
129 BaseCPU::init();
130
131 for (auto tc : threadContexts) {
132 // Initialise the ThreadContext's memory proxies
133 tc->initMemProxies(tc);
134
135 if (FullSystem && !params()->switched_out) {
136 // initialize CPU, including PC
137 TheISA::initCPU(tc, tc->contextId());
138 }
139 }
140}
141
142void
143BaseSimpleCPU::checkPcEventQueue()
144{
145 Addr oldpc, pc = threadInfo[curThread]->thread->instAddr();
146 do {
147 oldpc = pc;
148 system->pcEventQueue.service(threadContexts[curThread]);
149 pc = threadInfo[curThread]->thread->instAddr();
150 } while (oldpc != pc);
151}
152
153void
154BaseSimpleCPU::swapActiveThread()
155{
156 if (numThreads > 1) {
157 if ((!curStaticInst || !curStaticInst->isDelayedCommit()) &&
158 !threadInfo[curThread]->stayAtPC) {
159 // Swap active threads
160 if (!activeThreads.empty()) {
161 curThread = activeThreads.front();
162 activeThreads.pop_front();
163 activeThreads.push_back(curThread);
164 }
165 }
166 }
167}
168
169void
170BaseSimpleCPU::countInst()
171{
172 SimpleExecContext& t_info = *threadInfo[curThread];
173
174 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
175 t_info.numInst++;
176 t_info.numInsts++;
177
178 system->totalNumInsts++;
179 t_info.thread->funcExeInst++;
180 }
181 t_info.numOp++;
182 t_info.numOps++;
183}
184
185Counter
186BaseSimpleCPU::totalInsts() const
187{
188 Counter total_inst = 0;
189 for (auto& t_info : threadInfo) {
190 total_inst += t_info->numInst;
191 }
192
193 return total_inst;
194}
195
196Counter
197BaseSimpleCPU::totalOps() const
198{
199 Counter total_op = 0;
200 for (auto& t_info : threadInfo) {
201 total_op += t_info->numOp;
202 }
203
204 return total_op;
205}
206
207BaseSimpleCPU::~BaseSimpleCPU()
208{
209}
210
211void
212BaseSimpleCPU::haltContext(ThreadID thread_num)
213{
214 // for now, these are equivalent
215 suspendContext(thread_num);
216 updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
217}
218
219
220void
221BaseSimpleCPU::regStats()
222{
223 using namespace Stats;
224
225 BaseCPU::regStats();
226
227 for (ThreadID tid = 0; tid < numThreads; tid++) {
228 SimpleExecContext& t_info = *threadInfo[tid];
229
230 std::string thread_str = name();
231 if (numThreads > 1)
232 thread_str += ".thread" + std::to_string(tid);
233
234 t_info.numInsts
235 .name(thread_str + ".committedInsts")
236 .desc("Number of instructions committed")
237 ;
238
239 t_info.numOps
240 .name(thread_str + ".committedOps")
241 .desc("Number of ops (including micro ops) committed")
242 ;
243
244 t_info.numIntAluAccesses
245 .name(thread_str + ".num_int_alu_accesses")
246 .desc("Number of integer alu accesses")
247 ;
248
249 t_info.numFpAluAccesses
250 .name(thread_str + ".num_fp_alu_accesses")
251 .desc("Number of float alu accesses")
252 ;
253
254 t_info.numVecAluAccesses
255 .name(thread_str + ".num_vec_alu_accesses")
256 .desc("Number of vector alu accesses")
257 ;
258
259 t_info.numCallsReturns
260 .name(thread_str + ".num_func_calls")
261 .desc("number of times a function call or return occured")
262 ;
263
264 t_info.numCondCtrlInsts
265 .name(thread_str + ".num_conditional_control_insts")
266 .desc("number of instructions that are conditional controls")
267 ;
268
269 t_info.numIntInsts
270 .name(thread_str + ".num_int_insts")
271 .desc("number of integer instructions")
272 ;
273
274 t_info.numFpInsts
275 .name(thread_str + ".num_fp_insts")
276 .desc("number of float instructions")
277 ;
278
279 t_info.numVecInsts
280 .name(thread_str + ".num_vec_insts")
281 .desc("number of vector instructions")
282 ;
283
284 t_info.numIntRegReads
285 .name(thread_str + ".num_int_register_reads")
286 .desc("number of times the integer registers were read")
287 ;
288
289 t_info.numIntRegWrites
290 .name(thread_str + ".num_int_register_writes")
291 .desc("number of times the integer registers were written")
292 ;
293
294 t_info.numFpRegReads
295 .name(thread_str + ".num_fp_register_reads")
296 .desc("number of times the floating registers were read")
297 ;
298
299 t_info.numFpRegWrites
300 .name(thread_str + ".num_fp_register_writes")
301 .desc("number of times the floating registers were written")
302 ;
303
304 t_info.numVecRegReads
305 .name(thread_str + ".num_vec_register_reads")
306 .desc("number of times the vector registers were read")
307 ;
308
309 t_info.numVecRegWrites
310 .name(thread_str + ".num_vec_register_writes")
311 .desc("number of times the vector registers were written")
312 ;
313
314 t_info.numCCRegReads
315 .name(thread_str + ".num_cc_register_reads")
316 .desc("number of times the CC registers were read")
317 .flags(nozero)
318 ;
319
320 t_info.numCCRegWrites
321 .name(thread_str + ".num_cc_register_writes")
322 .desc("number of times the CC registers were written")
323 .flags(nozero)
324 ;
325
326 t_info.numMemRefs
327 .name(thread_str + ".num_mem_refs")
328 .desc("number of memory refs")
329 ;
330
331 t_info.numStoreInsts
332 .name(thread_str + ".num_store_insts")
333 .desc("Number of store instructions")
334 ;
335
336 t_info.numLoadInsts
337 .name(thread_str + ".num_load_insts")
338 .desc("Number of load instructions")
339 ;
340
341 t_info.notIdleFraction
342 .name(thread_str + ".not_idle_fraction")
343 .desc("Percentage of non-idle cycles")
344 ;
345
346 t_info.idleFraction
347 .name(thread_str + ".idle_fraction")
348 .desc("Percentage of idle cycles")
349 ;
350
351 t_info.numBusyCycles
352 .name(thread_str + ".num_busy_cycles")
353 .desc("Number of busy cycles")
354 ;
355
356 t_info.numIdleCycles
357 .name(thread_str + ".num_idle_cycles")
358 .desc("Number of idle cycles")
359 ;
360
361 t_info.icacheStallCycles
362 .name(thread_str + ".icache_stall_cycles")
363 .desc("ICache total stall cycles")
364 .prereq(t_info.icacheStallCycles)
365 ;
366
367 t_info.dcacheStallCycles
368 .name(thread_str + ".dcache_stall_cycles")
369 .desc("DCache total stall cycles")
370 .prereq(t_info.dcacheStallCycles)
371 ;
372
373 t_info.statExecutedInstType
374 .init(Enums::Num_OpClass)
375 .name(thread_str + ".op_class")
376 .desc("Class of executed instruction")
377 .flags(total | pdf | dist)
378 ;
379
380 for (unsigned i = 0; i < Num_OpClasses; ++i) {
381 t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
382 }
383
384 t_info.idleFraction = constant(1.0) - t_info.notIdleFraction;
385 t_info.numIdleCycles = t_info.idleFraction * numCycles;
386 t_info.numBusyCycles = t_info.notIdleFraction * numCycles;
387
388 t_info.numBranches
389 .name(thread_str + ".Branches")
390 .desc("Number of branches fetched")
391 .prereq(t_info.numBranches);
392
393 t_info.numPredictedBranches
394 .name(thread_str + ".predictedBranches")
395 .desc("Number of branches predicted as taken")
396 .prereq(t_info.numPredictedBranches);
397
398 t_info.numBranchMispred
399 .name(thread_str + ".BranchMispred")
400 .desc("Number of branch mispredictions")
401 .prereq(t_info.numBranchMispred);
402 }
403}
404
405void
406BaseSimpleCPU::resetStats()
407{
408 for (auto &thread_info : threadInfo) {
409 thread_info->notIdleFraction = (_status != Idle);
410 }
411}
412
413void
414BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
415{
416 assert(_status == Idle || _status == Running);
417
418 threadInfo[tid]->thread->serialize(cp);
419}
420
421void
422BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid)
423{
424 threadInfo[tid]->thread->unserialize(cp);
425}
426
427void
428change_thread_state(ThreadID tid, int activate, int priority)
429{
430}
431
432Addr
433BaseSimpleCPU::dbg_vtophys(Addr addr)
434{
435 return vtophys(threadContexts[curThread], addr);
436}
437
438void
439BaseSimpleCPU::wakeup(ThreadID tid)
440{
441 getCpuAddrMonitor(tid)->gotWakeup = true;
442
443 if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
444 DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
445 threadInfo[tid]->thread->activate();
446 }
447}
448
449void
450BaseSimpleCPU::checkForInterrupts()
451{
452 SimpleExecContext&t_info = *threadInfo[curThread];
453 SimpleThread* thread = t_info.thread;
454 ThreadContext* tc = thread->getTC();
455
456 if (checkInterrupts(tc)) {
457 Fault interrupt = interrupts[curThread]->getInterrupt(tc);
458
459 if (interrupt != NoFault) {
460 t_info.fetchOffset = 0;
461 interrupts[curThread]->updateIntrInfo(tc);
462 interrupt->invoke(tc);
463 thread->decoder.reset();
464 }
465 }
466}
467
468
469void
470BaseSimpleCPU::setupFetchRequest(const RequestPtr &req)
471{
472 SimpleExecContext &t_info = *threadInfo[curThread];
473 SimpleThread* thread = t_info.thread;
474
475 Addr instAddr = thread->instAddr();
476 Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
477
478 // set up memory request for instruction fetch
479 DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
480
481 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH,
482 instMasterId(), instAddr);
483}
484
485
486void
487BaseSimpleCPU::preExecute()
488{
489 SimpleExecContext &t_info = *threadInfo[curThread];
490 SimpleThread* thread = t_info.thread;
491
492 // maintain $r0 semantics
493 thread->setIntReg(ZeroReg, 0);
494#if THE_ISA == ALPHA_ISA
495 thread->setFloatReg(ZeroReg, 0);
496#endif // ALPHA_ISA
497
498 // check for instruction-count-based events
499 comInstEventQueue[curThread]->serviceEvents(t_info.numInst);
500 system->instEventQueue.serviceEvents(system->totalNumInsts);
501
502 // decode the instruction
503 inst = gtoh(inst);
504
505 TheISA::PCState pcState = thread->pcState();
506
507 if (isRomMicroPC(pcState.microPC())) {
508 t_info.stayAtPC = false;
509 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
510 curMacroStaticInst);
511 } else if (!curMacroStaticInst) {
512 //We're not in the middle of a macro instruction
513 StaticInstPtr instPtr = NULL;
514
515 TheISA::Decoder *decoder = &(thread->decoder);
516
517 //Predecode, ie bundle up an ExtMachInst
518 //If more fetch data is needed, pass it in.
519 Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset;
520 //if (decoder->needMoreBytes())
521 decoder->moreBytes(pcState, fetchPC, inst);
522 //else
523 // decoder->process();
524
525 //Decode an instruction if one is ready. Otherwise, we'll have to
526 //fetch beyond the MachInst at the current pc.
527 instPtr = decoder->decode(pcState);
528 if (instPtr) {
529 t_info.stayAtPC = false;
530 thread->pcState(pcState);
531 } else {
532 t_info.stayAtPC = true;
533 t_info.fetchOffset += sizeof(MachInst);
534 }
535
536 //If we decoded an instruction and it's microcoded, start pulling
537 //out micro ops
538 if (instPtr && instPtr->isMacroop()) {
539 curMacroStaticInst = instPtr;
540 curStaticInst =
541 curMacroStaticInst->fetchMicroop(pcState.microPC());
542 } else {
543 curStaticInst = instPtr;
544 }
545 } else {
546 //Read the next micro op from the macro op
547 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
548 }
549
550 //If we decoded an instruction this "tick", record information about it.
551 if (curStaticInst) {
552#if TRACING_ON
553 traceData = tracer->getInstRecord(curTick(), thread->getTC(),
554 curStaticInst, thread->pcState(), curMacroStaticInst);
555
556 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
557 curStaticInst->getName(), curStaticInst->machInst);
558#endif // TRACING_ON
559 }
560
561 if (branchPred && curStaticInst &&
562 curStaticInst->isControl()) {
563 // Use a fake sequence number since we only have one
564 // instruction in flight at the same time.
565 const InstSeqNum cur_sn(0);
566 t_info.predPC = thread->pcState();
567 const bool predict_taken(
568 branchPred->predict(curStaticInst, cur_sn, t_info.predPC,
569 curThread));
570
571 if (predict_taken)
572 ++t_info.numPredictedBranches;
573 }
574}
575
576void
577BaseSimpleCPU::postExecute()
578{
579 SimpleExecContext &t_info = *threadInfo[curThread];
580 SimpleThread* thread = t_info.thread;
581
582 assert(curStaticInst);
583
584 TheISA::PCState pc = threadContexts[curThread]->pcState();
585 Addr instAddr = pc.instAddr();
586 if (FullSystem && thread->profile) {
587 bool usermode = TheISA::inUserMode(threadContexts[curThread]);
588 thread->profilePC = usermode ? 1 : instAddr;
589 ProfileNode *node = thread->profile->consume(threadContexts[curThread],
590 curStaticInst);
591 if (node)
592 thread->profileNode = node;
593 }
594
595 if (curStaticInst->isMemRef()) {
596 t_info.numMemRefs++;
597 }
598
599 if (curStaticInst->isLoad()) {
600 ++t_info.numLoad;
601 comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad);
602 }
603
604 if (CPA::available()) {
605 CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr());
606 }
607
608 if (curStaticInst->isControl()) {
609 ++t_info.numBranches;
610 }
611
612 /* Power model statistics */
613 //integer alu accesses
614 if (curStaticInst->isInteger()){
615 t_info.numIntAluAccesses++;
616 t_info.numIntInsts++;
617 }
618
619 //float alu accesses
620 if (curStaticInst->isFloating()){
621 t_info.numFpAluAccesses++;
622 t_info.numFpInsts++;
623 }
624
625 //vector alu accesses
626 if (curStaticInst->isVector()){
627 t_info.numVecAluAccesses++;
628 t_info.numVecInsts++;
629 }
630
631 //number of function calls/returns to get window accesses
632 if (curStaticInst->isCall() || curStaticInst->isReturn()){
633 t_info.numCallsReturns++;
634 }
635
636 //the number of branch predictions that will be made
637 if (curStaticInst->isCondCtrl()){
638 t_info.numCondCtrlInsts++;
639 }
640
641 //result bus acceses
642 if (curStaticInst->isLoad()){
643 t_info.numLoadInsts++;
644 }
645
646 if (curStaticInst->isStore() || curStaticInst->isAtomic()){
647 t_info.numStoreInsts++;
648 }
649 /* End power model statistics */
650
651 t_info.statExecutedInstType[curStaticInst->opClass()]++;
652
653 if (FullSystem)
654 traceFunctions(instAddr);
655
656 if (traceData) {
657 traceData->dump();
658 delete traceData;
659 traceData = NULL;
660 }
661
662 // Call CPU instruction commit probes
663 probeInstCommit(curStaticInst, instAddr);
664}
665
666void
667BaseSimpleCPU::advancePC(const Fault &fault)
668{
669 SimpleExecContext &t_info = *threadInfo[curThread];
670 SimpleThread* thread = t_info.thread;
671
672 const bool branching(thread->pcState().branching());
673
674 //Since we're moving to a new pc, zero out the offset
675 t_info.fetchOffset = 0;
676 if (fault != NoFault) {
677 curMacroStaticInst = StaticInst::nullStaticInstPtr;
678 fault->invoke(threadContexts[curThread], curStaticInst);
679 thread->decoder.reset();
680 } else {
681 if (curStaticInst) {
682 if (curStaticInst->isLastMicroop())
683 curMacroStaticInst = StaticInst::nullStaticInstPtr;
684 TheISA::PCState pcState = thread->pcState();
685 TheISA::advancePC(pcState, curStaticInst);
686 thread->pcState(pcState);
687 }
688 }
689
690 if (branchPred && curStaticInst && curStaticInst->isControl()) {
691 // Use a fake sequence number since we only have one
692 // instruction in flight at the same time.
693 const InstSeqNum cur_sn(0);
694
695 if (t_info.predPC == thread->pcState()) {
696 // Correctly predicted branch
697 branchPred->update(cur_sn, curThread);
698 } else {
699 // Mis-predicted branch
700 branchPred->squash(cur_sn, thread->pcState(), branching, curThread);
701 ++t_info.numBranchMispred;
702 }
703 }
704}
705
706void
707BaseSimpleCPU::startup()
708{
709 BaseCPU::startup();
710 for (auto& t_info : threadInfo)
711 t_info->thread->startup();
712}