1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
58#include "cpu/simple/base.hh"
59#include "cpu/base.hh"
60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/profile.hh"
64#include "cpu/simple_thread.hh"
65#include "cpu/smt.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/thread_context.hh"
68#include "debug/Decode.hh"
69#include "debug/Fetch.hh"
70#include "debug/Quiesce.hh"

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80#include "sim/sim_object.hh"
81#include "sim/stats.hh"
82#include "sim/system.hh"
83
84using namespace std;
85using namespace TheISA;
86
87BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
88 : BaseCPU(p), traceData(NULL), thread(NULL)
89{
90 if (FullSystem)
91 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
92 p->isa[0]);
93 else
94 thread = new SimpleThread(this, /* thread_num */ 0, p->system,
95 p->workload[0], p->itb, p->dtb, p->isa[0]);
96

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281 .name(name() + ".dcache_retry_cycles")
282 .desc("DCache total retry cycles")
283 .prereq(dcacheRetryCycles)
284 ;
285
286 idleFraction = constant(1.0) - notIdleFraction;
287 numIdleCycles = idleFraction * numCycles;
288 numBusyCycles = (notIdleFraction)*numCycles;
289}
290
291void
292BaseSimpleCPU::resetStats()
293{
294// startNumInst = numInst;
295 notIdleFraction = (_status != Idle);
296}

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429#if TRACING_ON
430 traceData = tracer->getInstRecord(curTick(), tc,
431 curStaticInst, thread->pcState(), curMacroStaticInst);
432
433 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
434 curStaticInst->getName(), curStaticInst->machInst);
435#endif // TRACING_ON
436 }
437}
438
439void
440BaseSimpleCPU::postExecute()
441{
442 assert(curStaticInst);
443
444 TheISA::PCState pc = tc->pcState();

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459 ++numLoad;
460 comLoadEventQueue[0]->serviceEvents(numLoad);
461 }
462
463 if (CPA::available()) {
464 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
465 }
466
467 /* Power model statistics */
468 //integer alu accesses
469 if (curStaticInst->isInteger()){
470 numIntAluAccesses++;
471 numIntInsts++;
472 }
473
474 //float alu accesses

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502
503 if (traceData) {
504 traceData->dump();
505 delete traceData;
506 traceData = NULL;
507 }
508}
509
510
511void
512BaseSimpleCPU::advancePC(Fault fault)
513{
514 //Since we're moving to a new pc, zero out the offset
515 fetchOffset = 0;
516 if (fault != NoFault) {
517 curMacroStaticInst = StaticInst::nullStaticInstPtr;
518 fault->invoke(tc, curStaticInst);
519 thread->decoder.reset();
520 } else {
521 if (curStaticInst) {
522 if (curStaticInst->isLastMicroop())
523 curMacroStaticInst = StaticInst::nullStaticInstPtr;
524 TheISA::PCState pcState = thread->pcState();
525 TheISA::advancePC(pcState, curStaticInst);
526 thread->pcState(pcState);
527 }
528 }
529}
530
531void
532BaseSimpleCPU::startup()
533{
534 BaseCPU::startup();
535 thread->startup();
536}