1/*
2 * Copyright (c) 2010-2012,2015 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "cpu/simple/base.hh"
45
46#include "arch/kernel_stats.hh"
47#include "arch/stacktrace.hh"
48#include "arch/tlb.hh"
49#include "arch/utility.hh"
50#include "arch/vtophys.hh"
51#include "base/cp_annotate.hh"
52#include "base/cprintf.hh"
53#include "base/inifile.hh"
54#include "base/loader/symtab.hh"
55#include "base/misc.hh"
56#include "base/pollevent.hh"
57#include "base/trace.hh"
58#include "base/types.hh"
59#include "config/the_isa.hh"
60#include "cpu/base.hh"
61#include "cpu/checker/cpu.hh"
62#include "cpu/checker/thread_context.hh"
63#include "cpu/exetrace.hh"
64#include "cpu/pred/bpred_unit.hh"
65#include "cpu/profile.hh"
66#include "cpu/simple/exec_context.hh"
67#include "cpu/simple_thread.hh"
68#include "cpu/smt.hh"
69#include "cpu/static_inst.hh"
70#include "cpu/thread_context.hh"
71#include "debug/Decode.hh"
72#include "debug/Fetch.hh"
73#include "debug/Quiesce.hh"
74#include "mem/mem_object.hh"
75#include "mem/packet.hh"
76#include "mem/request.hh"
77#include "params/BaseSimpleCPU.hh"
78#include "sim/byteswap.hh"
79#include "sim/debug.hh"
80#include "sim/faults.hh"
81#include "sim/full_system.hh"
82#include "sim/sim_events.hh"
83#include "sim/sim_object.hh"
84#include "sim/stats.hh"
85#include "sim/system.hh"
86
87using namespace std;
88using namespace TheISA;
89
90BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
91 : BaseCPU(p),
92 curThread(0),
93 branchPred(p->branchPred),
94 traceData(NULL),
95 inst(),
96 _status(Idle)
97{
98 SimpleThread *thread;
99
100 for (unsigned i = 0; i < numThreads; i++) {
101 if (FullSystem) {
102 thread = new SimpleThread(this, i, p->system,
103 p->itb, p->dtb, p->isa[i]);
104 } else {
105 thread = new SimpleThread(this, i, p->system, p->workload[i],
106 p->itb, p->dtb, p->isa[i]);
107 }
108 threadInfo.push_back(new SimpleExecContext(this, thread));
109 ThreadContext *tc = thread->getTC();
110 threadContexts.push_back(tc);
111 }
112
113 if (p->checker) {
114 if (numThreads != 1)
115 fatal("Checker currently does not support SMT");
116
117 BaseCPU *temp_checker = p->checker;
118 checker = dynamic_cast<CheckerCPU *>(temp_checker);
119 checker->setSystem(p->system);
120 // Manipulate thread context
121 ThreadContext *cpu_tc = threadContexts[0];
122 threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
123 } else {
124 checker = NULL;
125 }
126}
127
128void
129BaseSimpleCPU::init()
130{
131 BaseCPU::init();
132
133 for (auto tc : threadContexts) {
134 // Initialise the ThreadContext's memory proxies
135 tc->initMemProxies(tc);
136
137 if (FullSystem && !params()->switched_out) {
138 // initialize CPU, including PC
139 TheISA::initCPU(tc, tc->contextId());
140 }
141 }
142}
143
144void
145BaseSimpleCPU::checkPcEventQueue()
146{
147 Addr oldpc, pc = threadInfo[curThread]->thread->instAddr();
148 do {
149 oldpc = pc;
150 system->pcEventQueue.service(threadContexts[curThread]);
151 pc = threadInfo[curThread]->thread->instAddr();
152 } while (oldpc != pc);
153}
154
155void
156BaseSimpleCPU::swapActiveThread()
157{
158 if (numThreads > 1) {
159 if ((!curStaticInst || !curStaticInst->isDelayedCommit()) &&
160 !threadInfo[curThread]->stayAtPC) {
161 // Swap active threads
162 if (!activeThreads.empty()) {
163 curThread = activeThreads.front();
164 activeThreads.pop_front();
165 activeThreads.push_back(curThread);
166 }
167 }
168 }
169}
170
171void
172BaseSimpleCPU::countInst()
173{
174 SimpleExecContext& t_info = *threadInfo[curThread];
175
176 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
177 t_info.numInst++;
178 t_info.numInsts++;
179 }
180 t_info.numOp++;
181 t_info.numOps++;
182
183 system->totalNumInsts++;
184 t_info.thread->funcExeInst++;
185}
186
187Counter
188BaseSimpleCPU::totalInsts() const
189{
190 Counter total_inst = 0;
191 for (auto& t_info : threadInfo) {
192 total_inst += t_info->numInst;
193 }
194
195 return total_inst;
196}
197
198Counter
199BaseSimpleCPU::totalOps() const
200{
201 Counter total_op = 0;
202 for (auto& t_info : threadInfo) {
203 total_op += t_info->numOp;
204 }
205
206 return total_op;
207}
208
209BaseSimpleCPU::~BaseSimpleCPU()
210{
211}
212
213void
214BaseSimpleCPU::haltContext(ThreadID thread_num)
215{
216 // for now, these are equivalent
217 suspendContext(thread_num);
218}
219
220
221void
222BaseSimpleCPU::regStats()
223{
224 using namespace Stats;
225
226 BaseCPU::regStats();
227
228 for (ThreadID tid = 0; tid < numThreads; tid++) {
229 SimpleExecContext& t_info = *threadInfo[tid];
230
231 std::string thread_str = name();
232 if (numThreads > 1)
233 thread_str += ".thread" + std::to_string(tid);
234
235 t_info.numInsts
236 .name(thread_str + ".committedInsts")
237 .desc("Number of instructions committed")
238 ;
239
240 t_info.numOps
241 .name(thread_str + ".committedOps")
242 .desc("Number of ops (including micro ops) committed")
243 ;
244
245 t_info.numIntAluAccesses
246 .name(thread_str + ".num_int_alu_accesses")
247 .desc("Number of integer alu accesses")
248 ;
249
250 t_info.numFpAluAccesses
251 .name(thread_str + ".num_fp_alu_accesses")
252 .desc("Number of float alu accesses")
253 ;
254
255 t_info.numCallsReturns
256 .name(thread_str + ".num_func_calls")
257 .desc("number of times a function call or return occured")
258 ;
259
260 t_info.numCondCtrlInsts
261 .name(thread_str + ".num_conditional_control_insts")
262 .desc("number of instructions that are conditional controls")
263 ;
264
265 t_info.numIntInsts
266 .name(thread_str + ".num_int_insts")
267 .desc("number of integer instructions")
268 ;
269
270 t_info.numFpInsts
271 .name(thread_str + ".num_fp_insts")
272 .desc("number of float instructions")
273 ;
274
275 t_info.numIntRegReads
276 .name(thread_str + ".num_int_register_reads")
277 .desc("number of times the integer registers were read")
278 ;
279
280 t_info.numIntRegWrites
281 .name(thread_str + ".num_int_register_writes")
282 .desc("number of times the integer registers were written")
283 ;
284
285 t_info.numFpRegReads
286 .name(thread_str + ".num_fp_register_reads")
287 .desc("number of times the floating registers were read")
288 ;
289
290 t_info.numFpRegWrites
291 .name(thread_str + ".num_fp_register_writes")
292 .desc("number of times the floating registers were written")
293 ;
294
295 t_info.numVecRegReads
296 .name(thread_str + ".num_vec_register_reads")
297 .desc("number of times the vector registers were read")
298 ;
299
300 t_info.numVecRegWrites
301 .name(thread_str + ".num_vec_register_writes")
302 .desc("number of times the vector registers were written")
303 ;
304
305 t_info.numCCRegReads
306 .name(thread_str + ".num_cc_register_reads")
307 .desc("number of times the CC registers were read")
308 .flags(nozero)
309 ;
310
311 t_info.numCCRegWrites
312 .name(thread_str + ".num_cc_register_writes")
313 .desc("number of times the CC registers were written")
314 .flags(nozero)
315 ;
316
317 t_info.numMemRefs
318 .name(thread_str + ".num_mem_refs")
319 .desc("number of memory refs")
320 ;
321
322 t_info.numStoreInsts
323 .name(thread_str + ".num_store_insts")
324 .desc("Number of store instructions")
325 ;
326
327 t_info.numLoadInsts
328 .name(thread_str + ".num_load_insts")
329 .desc("Number of load instructions")
330 ;
331
332 t_info.notIdleFraction
333 .name(thread_str + ".not_idle_fraction")
334 .desc("Percentage of non-idle cycles")
335 ;
336
337 t_info.idleFraction
338 .name(thread_str + ".idle_fraction")
339 .desc("Percentage of idle cycles")
340 ;
341
342 t_info.numBusyCycles
343 .name(thread_str + ".num_busy_cycles")
344 .desc("Number of busy cycles")
345 ;
346
347 t_info.numIdleCycles
348 .name(thread_str + ".num_idle_cycles")
349 .desc("Number of idle cycles")
350 ;
351
352 t_info.icacheStallCycles
353 .name(thread_str + ".icache_stall_cycles")
354 .desc("ICache total stall cycles")
355 .prereq(t_info.icacheStallCycles)
356 ;
357
358 t_info.dcacheStallCycles
359 .name(thread_str + ".dcache_stall_cycles")
360 .desc("DCache total stall cycles")
361 .prereq(t_info.dcacheStallCycles)
362 ;
363
364 t_info.statExecutedInstType
365 .init(Enums::Num_OpClass)
366 .name(thread_str + ".op_class")
367 .desc("Class of executed instruction")
368 .flags(total | pdf | dist)
369 ;
370
371 for (unsigned i = 0; i < Num_OpClasses; ++i) {
372 t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
373 }
374
375 t_info.idleFraction = constant(1.0) - t_info.notIdleFraction;
376 t_info.numIdleCycles = t_info.idleFraction * numCycles;
377 t_info.numBusyCycles = t_info.notIdleFraction * numCycles;
378
379 t_info.numBranches
380 .name(thread_str + ".Branches")
381 .desc("Number of branches fetched")
382 .prereq(t_info.numBranches);
383
384 t_info.numPredictedBranches
385 .name(thread_str + ".predictedBranches")
386 .desc("Number of branches predicted as taken")
387 .prereq(t_info.numPredictedBranches);
388
389 t_info.numBranchMispred
390 .name(thread_str + ".BranchMispred")
391 .desc("Number of branch mispredictions")
392 .prereq(t_info.numBranchMispred);
393 }
394}
395
396void
397BaseSimpleCPU::resetStats()
398{
399 for (auto &thread_info : threadInfo) {
400 thread_info->notIdleFraction = (_status != Idle);
401 }
402}
403
404void
405BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
406{
407 assert(_status == Idle || _status == Running);
408
409 threadInfo[tid]->thread->serialize(cp);
410}
411
412void
413BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid)
414{
415 threadInfo[tid]->thread->unserialize(cp);
416}
417
418void
419change_thread_state(ThreadID tid, int activate, int priority)
420{
421}
422
423Addr
424BaseSimpleCPU::dbg_vtophys(Addr addr)
425{
426 return vtophys(threadContexts[curThread], addr);
427}
428
429void
430BaseSimpleCPU::wakeup(ThreadID tid)
431{
432 getCpuAddrMonitor(tid)->gotWakeup = true;
433
434 if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
435 DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
436 threadInfo[tid]->thread->activate();
437 }
438}
439
440void
441BaseSimpleCPU::checkForInterrupts()
442{
443 SimpleExecContext&t_info = *threadInfo[curThread];
444 SimpleThread* thread = t_info.thread;
445 ThreadContext* tc = thread->getTC();
446
447 if (checkInterrupts(tc)) {
448 Fault interrupt = interrupts[curThread]->getInterrupt(tc);
449
450 if (interrupt != NoFault) {
451 t_info.fetchOffset = 0;
452 interrupts[curThread]->updateIntrInfo(tc);
453 interrupt->invoke(tc);
454 thread->decoder.reset();
455 }
456 }
457}
458
459
460void
461BaseSimpleCPU::setupFetchRequest(Request *req)
462{
463 SimpleExecContext &t_info = *threadInfo[curThread];
464 SimpleThread* thread = t_info.thread;
465
466 Addr instAddr = thread->instAddr();
467
468 // set up memory request for instruction fetch
469 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
470
471 Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
472 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
473 instAddr);
474}
475
476
477void
478BaseSimpleCPU::preExecute()
479{
480 SimpleExecContext &t_info = *threadInfo[curThread];
481 SimpleThread* thread = t_info.thread;
482
483 // maintain $r0 semantics
484 thread->setIntReg(ZeroReg, 0);
485#if THE_ISA == ALPHA_ISA
486 thread->setFloatReg(ZeroReg, 0.0);
487#endif // ALPHA_ISA
488
489 // check for instruction-count-based events
490 comInstEventQueue[curThread]->serviceEvents(t_info.numInst);
491 system->instEventQueue.serviceEvents(system->totalNumInsts);
492
493 // decode the instruction
494 inst = gtoh(inst);
495
496 TheISA::PCState pcState = thread->pcState();
497
498 if (isRomMicroPC(pcState.microPC())) {
499 t_info.stayAtPC = false;
500 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
501 curMacroStaticInst);
502 } else if (!curMacroStaticInst) {
503 //We're not in the middle of a macro instruction
504 StaticInstPtr instPtr = NULL;
505
506 TheISA::Decoder *decoder = &(thread->decoder);
507
508 //Predecode, ie bundle up an ExtMachInst
509 //If more fetch data is needed, pass it in.
510 Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset;
511 //if (decoder->needMoreBytes())
512 decoder->moreBytes(pcState, fetchPC, inst);
513 //else
514 // decoder->process();
515
516 //Decode an instruction if one is ready. Otherwise, we'll have to
517 //fetch beyond the MachInst at the current pc.
518 instPtr = decoder->decode(pcState);
519 if (instPtr) {
520 t_info.stayAtPC = false;
521 thread->pcState(pcState);
522 } else {
523 t_info.stayAtPC = true;
524 t_info.fetchOffset += sizeof(MachInst);
525 }
526
527 //If we decoded an instruction and it's microcoded, start pulling
528 //out micro ops
529 if (instPtr && instPtr->isMacroop()) {
530 curMacroStaticInst = instPtr;
531 curStaticInst =
532 curMacroStaticInst->fetchMicroop(pcState.microPC());
533 } else {
534 curStaticInst = instPtr;
535 }
536 } else {
537 //Read the next micro op from the macro op
538 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
539 }
540
541 //If we decoded an instruction this "tick", record information about it.
542 if (curStaticInst) {
543#if TRACING_ON
544 traceData = tracer->getInstRecord(curTick(), thread->getTC(),
545 curStaticInst, thread->pcState(), curMacroStaticInst);
546
547 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
548 curStaticInst->getName(), curStaticInst->machInst);
549#endif // TRACING_ON
550 }
551
552 if (branchPred && curStaticInst &&
553 curStaticInst->isControl()) {
554 // Use a fake sequence number since we only have one
555 // instruction in flight at the same time.
556 const InstSeqNum cur_sn(0);
557 t_info.predPC = thread->pcState();
558 const bool predict_taken(
559 branchPred->predict(curStaticInst, cur_sn, t_info.predPC,
560 curThread));
561
562 if (predict_taken)
563 ++t_info.numPredictedBranches;
564 }
565}
566
567void
568BaseSimpleCPU::postExecute()
569{
570 SimpleExecContext &t_info = *threadInfo[curThread];
571 SimpleThread* thread = t_info.thread;
572
573 assert(curStaticInst);
574
575 TheISA::PCState pc = threadContexts[curThread]->pcState();
576 Addr instAddr = pc.instAddr();
577 if (FullSystem && thread->profile) {
578 bool usermode = TheISA::inUserMode(threadContexts[curThread]);
579 thread->profilePC = usermode ? 1 : instAddr;
580 ProfileNode *node = thread->profile->consume(threadContexts[curThread],
581 curStaticInst);
582 if (node)
583 thread->profileNode = node;
584 }
585
586 if (curStaticInst->isMemRef()) {
587 t_info.numMemRefs++;
588 }
589
590 if (curStaticInst->isLoad()) {
591 ++t_info.numLoad;
592 comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad);
593 }
594
595 if (CPA::available()) {
596 CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr());
597 }
598
599 if (curStaticInst->isControl()) {
600 ++t_info.numBranches;
601 }
602
603 /* Power model statistics */
604 //integer alu accesses
605 if (curStaticInst->isInteger()){
606 t_info.numIntAluAccesses++;
607 t_info.numIntInsts++;
608 }
609
610 //float alu accesses
611 if (curStaticInst->isFloating()){
612 t_info.numFpAluAccesses++;
613 t_info.numFpInsts++;
614 }
615
616 //number of function calls/returns to get window accesses
617 if (curStaticInst->isCall() || curStaticInst->isReturn()){
618 t_info.numCallsReturns++;
619 }
620
621 //the number of branch predictions that will be made
622 if (curStaticInst->isCondCtrl()){
623 t_info.numCondCtrlInsts++;
624 }
625
626 //result bus acceses
627 if (curStaticInst->isLoad()){
628 t_info.numLoadInsts++;
629 }
630
631 if (curStaticInst->isStore()){
632 t_info.numStoreInsts++;
633 }
634 /* End power model statistics */
635
636 t_info.statExecutedInstType[curStaticInst->opClass()]++;
637
638 if (FullSystem)
639 traceFunctions(instAddr);
640
641 if (traceData) {
642 traceData->dump();
643 delete traceData;
644 traceData = NULL;
645 }
646
647 // Call CPU instruction commit probes
648 probeInstCommit(curStaticInst);
649}
650
651void
652BaseSimpleCPU::advancePC(const Fault &fault)
653{
654 SimpleExecContext &t_info = *threadInfo[curThread];
655 SimpleThread* thread = t_info.thread;
656
657 const bool branching(thread->pcState().branching());
658
659 //Since we're moving to a new pc, zero out the offset
660 t_info.fetchOffset = 0;
661 if (fault != NoFault) {
662 curMacroStaticInst = StaticInst::nullStaticInstPtr;
663 fault->invoke(threadContexts[curThread], curStaticInst);
664 thread->decoder.reset();
665 } else {
666 if (curStaticInst) {
667 if (curStaticInst->isLastMicroop())
668 curMacroStaticInst = StaticInst::nullStaticInstPtr;
669 TheISA::PCState pcState = thread->pcState();
670 TheISA::advancePC(pcState, curStaticInst);
671 thread->pcState(pcState);
672 }
673 }
674
675 if (branchPred && curStaticInst && curStaticInst->isControl()) {
676 // Use a fake sequence number since we only have one
677 // instruction in flight at the same time.
678 const InstSeqNum cur_sn(0);
679
680 if (t_info.predPC == thread->pcState()) {
681 // Correctly predicted branch
682 branchPred->update(cur_sn, curThread);
683 } else {
684 // Mis-predicted branch
685 branchPred->squash(cur_sn, thread->pcState(), branching, curThread);
686 ++t_info.numBranchMispred;
687 }
688 }
689}
690
691void
692BaseSimpleCPU::startup()
693{
694 BaseCPU::startup();
695 for (auto& t_info : threadInfo)
696 t_info->thread->startup();
697}