atomic.hh (9704:dd6a9d314e40) atomic.hh (10030:b531e328342d)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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142 * also provides an implementation for the purely virtual timing
143 * functions and panics on either of these.
144 */
145 class AtomicCPUPort : public MasterPort
146 {
147
148 public:
149
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 133 unchanged lines hidden (view full) ---

142 * also provides an implementation for the purely virtual timing
143 * functions and panics on either of these.
144 */
145 class AtomicCPUPort : public MasterPort
146 {
147
148 public:
149
150 AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
150 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
151 : MasterPort(_name, _cpu)
152 { }
153
154 protected:
151 : MasterPort(_name, _cpu)
152 { }
153
154 protected:
155 virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
155
156
156 virtual Tick recvAtomicSnoop(PacketPtr pkt)
157 {
158 // Snooping a coherence request, just return
159 return 0;
160 }
161
162 bool recvTimingResp(PacketPtr pkt)
163 {
164 panic("Atomic CPU doesn't expect recvTimingResp!\n");
165 return true;
166 }
167
168 void recvRetry()
169 {
170 panic("Atomic CPU doesn't expect recvRetry!\n");
171 }
172
173 };
174
157 bool recvTimingResp(PacketPtr pkt)
158 {
159 panic("Atomic CPU doesn't expect recvTimingResp!\n");
160 return true;
161 }
162
163 void recvRetry()
164 {
165 panic("Atomic CPU doesn't expect recvRetry!\n");
166 }
167
168 };
169
170 class AtomicCPUDPort : public AtomicCPUPort
171 {
172
173 public:
174
175 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
176 : AtomicCPUPort(_name, _cpu), cpu(_cpu)
177 {
178 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
179 }
180
181 bool isSnooping() const { return true; }
182
183 Addr cacheBlockMask;
184 protected:
185 BaseSimpleCPU *cpu;
186
187 virtual Tick recvAtomicSnoop(PacketPtr pkt);
188 virtual void recvFunctionalSnoop(PacketPtr pkt);
189 };
190
191
175 AtomicCPUPort icachePort;
192 AtomicCPUPort icachePort;
176 AtomicCPUPort dcachePort;
193 AtomicCPUDPort dcachePort;
177
178 bool fastmem;
179 Request ifetch_req;
180 Request data_read_req;
181 Request data_write_req;
182
183 bool dcache_access;
184 Tick dcache_latency;

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195 bool fastmem;
196 Request ifetch_req;
197 Request data_read_req;
198 Request data_write_req;
199
200 bool dcache_access;
201 Tick dcache_latency;

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