atomic.hh (9523:b8c8437f71d9) atomic.hh (9608:e2b6b86fda03)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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111 * Try to complete a drain request.
112 *
113 * @returns true if the CPU is drained, false otherwise.
114 */
115 bool tryCompleteDrain();
116
117 /**
118 * An AtomicCPUPort overrides the default behaviour of the
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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111 * Try to complete a drain request.
112 *
113 * @returns true if the CPU is drained, false otherwise.
114 */
115 bool tryCompleteDrain();
116
117 /**
118 * An AtomicCPUPort overrides the default behaviour of the
119 * recvAtomic and ignores the packet instead of panicking.
119 * recvAtomicSnoop and ignores the packet instead of panicking. It
120 * also provides an implementation for the purely virtual timing
121 * functions and panics on either of these.
120 */
122 */
121 class AtomicCPUPort : public CpuPort
123 class AtomicCPUPort : public MasterPort
122 {
123
124 public:
125
126 AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
124 {
125
126 public:
127
128 AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
127 : CpuPort(_name, _cpu)
129 : MasterPort(_name, _cpu)
128 { }
129
130 protected:
131
132 virtual Tick recvAtomicSnoop(PacketPtr pkt)
133 {
134 // Snooping a coherence request, just return
135 return 0;
136 }
137
130 { }
131
132 protected:
133
134 virtual Tick recvAtomicSnoop(PacketPtr pkt)
135 {
136 // Snooping a coherence request, just return
137 return 0;
138 }
139
140 bool recvTimingResp(PacketPtr pkt)
141 {
142 panic("Atomic CPU doesn't expect recvTimingResp!\n");
143 return true;
144 }
145
146 void recvRetry()
147 {
148 panic("Atomic CPU doesn't expect recvRetry!\n");
149 }
150
138 };
139
140 AtomicCPUPort icachePort;
141 AtomicCPUPort dcachePort;
142
143 bool fastmem;
144 Request ifetch_req;
145 Request data_read_req;
146 Request data_write_req;
147
148 bool dcache_access;
149 Tick dcache_latency;
150
151 protected:
152
153 /** Return a reference to the data port. */
151 };
152
153 AtomicCPUPort icachePort;
154 AtomicCPUPort dcachePort;
155
156 bool fastmem;
157 Request ifetch_req;
158 Request data_read_req;
159 Request data_write_req;
160
161 bool dcache_access;
162 Tick dcache_latency;
163
164 protected:
165
166 /** Return a reference to the data port. */
154 virtual CpuPort &getDataPort() { return dcachePort; }
167 virtual MasterPort &getDataPort() { return dcachePort; }
155
156 /** Return a reference to the instruction port. */
168
169 /** Return a reference to the instruction port. */
157 virtual CpuPort &getInstPort() { return icachePort; }
170 virtual MasterPort &getInstPort() { return icachePort; }
158
159 public:
160
161 unsigned int drain(DrainManager *drain_manager);
162 void drainResume();
163
164 void switchOut();
165 void takeOverFrom(BaseCPU *oldCPU);

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172 public:
173
174 unsigned int drain(DrainManager *drain_manager);
175 void drainResume();
176
177 void switchOut();
178 void takeOverFrom(BaseCPU *oldCPU);

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