atomic.hh (4192:7accc6365bb9) | atomic.hh (4475:fb185cc1c845) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 90 unchanged lines hidden (view full) --- 99 100 virtual void recvFunctional(PacketPtr pkt); 101 102 virtual void recvStatusChange(Status status); 103 104 virtual void recvRetry(); 105 106 virtual void getDeviceAddressRanges(AddrRangeList &resp, | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 90 unchanged lines hidden (view full) --- 99 100 virtual void recvFunctional(PacketPtr pkt); 101 102 virtual void recvStatusChange(Status status); 103 104 virtual void recvRetry(); 105 106 virtual void getDeviceAddressRanges(AddrRangeList &resp, |
107 AddrRangeList &snoop) 108 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } | 107 bool &snoop) 108 { resp.clear(); snoop = true; } |
109 110 }; 111 CpuPort icachePort; 112 113 class DcachePort : public CpuPort 114 { 115 public: 116 DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu) --- 40 unchanged lines hidden --- | 109 110 }; 111 CpuPort icachePort; 112 113 class DcachePort : public CpuPort 114 { 115 public: 116 DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu) --- 40 unchanged lines hidden --- |