atomic.hh (12749:223c83ed9979) | atomic.hh (13012:5fbc6b9c64bc) |
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1/* | 1/* |
2 * Copyright (c) 2012-2013,2015 ARM Limited | 2 * Copyright (c) 2012-2013, 2015, 2018 ARM Limited |
3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 42 unchanged lines hidden (view full) --- 53{ 54 public: 55 56 AtomicSimpleCPU(AtomicSimpleCPUParams *params); 57 virtual ~AtomicSimpleCPU(); 58 59 void init() override; 60 | 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 42 unchanged lines hidden (view full) --- 53{ 54 public: 55 56 AtomicSimpleCPU(AtomicSimpleCPUParams *params); 57 virtual ~AtomicSimpleCPU(); 58 59 void init() override; 60 |
61 private: | 61 protected: |
62 63 EventFunctionWrapper tickEvent; 64 65 const int width; 66 bool locked; 67 const bool simulate_data_stalls; 68 const bool simulate_inst_stalls; 69 --- 28 unchanged lines hidden (view full) --- 98 99 /** 100 * Try to complete a drain request. 101 * 102 * @returns true if the CPU is drained, false otherwise. 103 */ 104 bool tryCompleteDrain(); 105 | 62 63 EventFunctionWrapper tickEvent; 64 65 const int width; 66 bool locked; 67 const bool simulate_data_stalls; 68 const bool simulate_inst_stalls; 69 --- 28 unchanged lines hidden (view full) --- 98 99 /** 100 * Try to complete a drain request. 101 * 102 * @returns true if the CPU is drained, false otherwise. 103 */ 104 bool tryCompleteDrain(); 105 |
106 virtual Tick sendPacket(MasterPort &port, const PacketPtr &pkt); 107 |
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106 /** 107 * An AtomicCPUPort overrides the default behaviour of the 108 * recvAtomicSnoop and ignores the packet instead of panicking. It 109 * also provides an implementation for the purely virtual timing 110 * functions and panics on either of these. 111 */ 112 class AtomicCPUPort : public MasterPort 113 { --- 18 unchanged lines hidden (view full) --- 132 } 133 134 }; 135 136 class AtomicCPUDPort : public AtomicCPUPort 137 { 138 139 public: | 108 /** 109 * An AtomicCPUPort overrides the default behaviour of the 110 * recvAtomicSnoop and ignores the packet instead of panicking. It 111 * also provides an implementation for the purely virtual timing 112 * functions and panics on either of these. 113 */ 114 class AtomicCPUPort : public MasterPort 115 { --- 18 unchanged lines hidden (view full) --- 134 } 135 136 }; 137 138 class AtomicCPUDPort : public AtomicCPUPort 139 { 140 141 public: |
140 | |
141 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) 142 : AtomicCPUPort(_name, _cpu), cpu(_cpu) 143 { 144 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 145 } 146 147 bool isSnooping() const { return true; } 148 --- 4 unchanged lines hidden (view full) --- 153 virtual Tick recvAtomicSnoop(PacketPtr pkt); 154 virtual void recvFunctionalSnoop(PacketPtr pkt); 155 }; 156 157 158 AtomicCPUPort icachePort; 159 AtomicCPUDPort dcachePort; 160 | 142 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) 143 : AtomicCPUPort(_name, _cpu), cpu(_cpu) 144 { 145 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 146 } 147 148 bool isSnooping() const { return true; } 149 --- 4 unchanged lines hidden (view full) --- 154 virtual Tick recvAtomicSnoop(PacketPtr pkt); 155 virtual void recvFunctionalSnoop(PacketPtr pkt); 156 }; 157 158 159 AtomicCPUPort icachePort; 160 AtomicCPUDPort dcachePort; 161 |
161 bool fastmem; | 162 |
162 RequestPtr ifetch_req; 163 RequestPtr data_read_req; 164 RequestPtr data_write_req; 165 166 bool dcache_access; 167 Tick dcache_latency; 168 169 /** Probe Points. */ --- 45 unchanged lines hidden --- | 163 RequestPtr ifetch_req; 164 RequestPtr data_read_req; 165 RequestPtr data_write_req; 166 167 bool dcache_access; 168 Tick dcache_latency; 169 170 /** Probe Points. */ --- 45 unchanged lines hidden --- |