atomic.hh (11168:f98eb2da15a4) atomic.hh (11169:44b5c183c3cd)
1/*
2 * Copyright (c) 2012-2013,2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50
51class AtomicSimpleCPU : public BaseSimpleCPU
52{
53 public:
54
55 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
56 virtual ~AtomicSimpleCPU();
57
1/*
2 * Copyright (c) 2012-2013,2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 41 unchanged lines hidden (view full) ---

50
51class AtomicSimpleCPU : public BaseSimpleCPU
52{
53 public:
54
55 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
56 virtual ~AtomicSimpleCPU();
57
58 virtual void init();
58 void init() override;
59
60 private:
61
62 struct TickEvent : public Event
63 {
64 AtomicSimpleCPU *cpu;
65
66 TickEvent(AtomicSimpleCPU *c);

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176 Tick dcache_latency;
177
178 /** Probe Points. */
179 ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
180
181 protected:
182
183 /** Return a reference to the data port. */
59
60 private:
61
62 struct TickEvent : public Event
63 {
64 AtomicSimpleCPU *cpu;
65
66 TickEvent(AtomicSimpleCPU *c);

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176 Tick dcache_latency;
177
178 /** Probe Points. */
179 ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
180
181 protected:
182
183 /** Return a reference to the data port. */
184 virtual MasterPort &getDataPort() { return dcachePort; }
184 MasterPort &getDataPort() override { return dcachePort; }
185
186 /** Return a reference to the instruction port. */
185
186 /** Return a reference to the instruction port. */
187 virtual MasterPort &getInstPort() { return icachePort; }
187 MasterPort &getInstPort() override { return icachePort; }
188
189 /** Perform snoop for other cpu-local thread contexts. */
190 void threadSnoop(PacketPtr pkt, ThreadID sender);
191
192 public:
193
194 DrainState drain() override;
195 void drainResume() override;
196
188
189 /** Perform snoop for other cpu-local thread contexts. */
190 void threadSnoop(PacketPtr pkt, ThreadID sender);
191
192 public:
193
194 DrainState drain() override;
195 void drainResume() override;
196
197 void switchOut();
198 void takeOverFrom(BaseCPU *oldCPU);
197 void switchOut() override;
198 void takeOverFrom(BaseCPU *oldCPU) override;
199
199
200 void verifyMemoryMode() const;
200 void verifyMemoryMode() const override;
201
201
202 virtual void activateContext(ThreadID thread_num);
203 virtual void suspendContext(ThreadID thread_num);
202 void activateContext(ThreadID thread_num) override;
203 void suspendContext(ThreadID thread_num) override;
204
204
205 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
205 Fault readMem(Addr addr, uint8_t *data, unsigned size,
206 unsigned flags) override;
206
207 Fault writeMem(uint8_t *data, unsigned size,
207
208 Fault writeMem(uint8_t *data, unsigned size,
208 Addr addr, unsigned flags, uint64_t *res);
209 Addr addr, unsigned flags, uint64_t *res) override;
209
210
210 virtual void regProbePoints();
211 void regProbePoints() override;
211
212 /**
213 * Print state of address in memory system via PrintReq (for
214 * debugging).
215 */
216 void printAddr(Addr a);
217};
218
219#endif // __CPU_SIMPLE_ATOMIC_HH__
212
213 /**
214 * Print state of address in memory system via PrintReq (for
215 * debugging).
216 */
217 void printAddr(Addr a);
218};
219
220#endif // __CPU_SIMPLE_ATOMIC_HH__