atomic.hh (10030:b531e328342d) atomic.hh (10381:ab8b8601b6ff)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __CPU_SIMPLE_ATOMIC_HH__
44#define __CPU_SIMPLE_ATOMIC_HH__
45
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __CPU_SIMPLE_ATOMIC_HH__
44#define __CPU_SIMPLE_ATOMIC_HH__
45
46#include "base/hashmap.hh"
47#include "cpu/simple/base.hh"
48#include "params/AtomicSimpleCPU.hh"
46#include "cpu/simple/base.hh"
47#include "params/AtomicSimpleCPU.hh"
48#include "sim/probe/probe.hh"
49
49
50/**
51 * Start and end address of basic block for SimPoint profiling.
52 * This structure is used to look up the hash table of BBVs.
53 * - first: PC of first inst in basic block
54 * - second: PC of last inst in basic block
55 */
56typedef std::pair<Addr, Addr> BasicBlockRange;
57
58/** Overload hash function for BasicBlockRange type */
59__hash_namespace_begin
60template <>
61struct hash<BasicBlockRange>
62{
63 public:
64 size_t operator()(const BasicBlockRange &bb) const {
65 return hash<Addr>()(bb.first + bb.second);
66 }
67};
68__hash_namespace_end
69
70
71class AtomicSimpleCPU : public BaseSimpleCPU
72{
73 public:
74
75 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
76 virtual ~AtomicSimpleCPU();
77
78 virtual void init();

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195 bool fastmem;
196 Request ifetch_req;
197 Request data_read_req;
198 Request data_write_req;
199
200 bool dcache_access;
201 Tick dcache_latency;
202
50class AtomicSimpleCPU : public BaseSimpleCPU
51{
52 public:
53
54 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
55 virtual ~AtomicSimpleCPU();
56
57 virtual void init();

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174 bool fastmem;
175 Request ifetch_req;
176 Request data_read_req;
177 Request data_write_req;
178
179 bool dcache_access;
180 Tick dcache_latency;
181
203 /**
204 * Profile basic blocks for SimPoints.
205 * Called at every macro inst to increment basic block inst counts and
206 * to profile block if end of block.
207 */
208 void profileSimPoint();
182 /** Probe Points. */
183 ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
209
184
210 /** Data structures for SimPoints BBV generation
211 * @{
212 */
213
214 /** Whether SimPoint BBV profiling is enabled */
215 const bool simpoint;
216 /** SimPoint profiling interval size in instructions */
217 const uint64_t intervalSize;
218
219 /** Inst count in current basic block */
220 uint64_t intervalCount;
221 /** Excess inst count from previous interval*/
222 uint64_t intervalDrift;
223 /** Pointer to SimPoint BBV output stream */
224 std::ostream *simpointStream;
225
226 /** Basic Block information */
227 struct BBInfo {
228 /** Unique ID */
229 uint64_t id;
230 /** Num of static insts in BB */
231 uint64_t insts;
232 /** Accumulated dynamic inst count executed by BB */
233 uint64_t count;
234 };
235
236 /** Hash table containing all previously seen basic blocks */
237 m5::hash_map<BasicBlockRange, BBInfo> bbMap;
238 /** Currently executing basic block */
239 BasicBlockRange currentBBV;
240 /** inst count in current basic block */
241 uint64_t currentBBVInstCount;
242
243 /** @}
244 * End of data structures for SimPoints BBV generation
245 */
246
247 protected:
248
249 /** Return a reference to the data port. */
250 virtual MasterPort &getDataPort() { return dcachePort; }
251
252 /** Return a reference to the instruction port. */
253 virtual MasterPort &getInstPort() { return icachePort; }
254

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265 virtual void activateContext(ThreadID thread_num, Cycles delay);
266 virtual void suspendContext(ThreadID thread_num);
267
268 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
269
270 Fault writeMem(uint8_t *data, unsigned size,
271 Addr addr, unsigned flags, uint64_t *res);
272
185 protected:
186
187 /** Return a reference to the data port. */
188 virtual MasterPort &getDataPort() { return dcachePort; }
189
190 /** Return a reference to the instruction port. */
191 virtual MasterPort &getInstPort() { return icachePort; }
192

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203 virtual void activateContext(ThreadID thread_num, Cycles delay);
204 virtual void suspendContext(ThreadID thread_num);
205
206 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
207
208 Fault writeMem(uint8_t *data, unsigned size,
209 Addr addr, unsigned flags, uint64_t *res);
210
211 virtual void regProbePoints();
212
273 /**
274 * Print state of address in memory system via PrintReq (for
275 * debugging).
276 */
277 void printAddr(Addr a);
278};
279
280#endif // __CPU_SIMPLE_ATOMIC_HH__
213 /**
214 * Print state of address in memory system via PrintReq (for
215 * debugging).
216 */
217 void printAddr(Addr a);
218};
219
220#endif // __CPU_SIMPLE_ATOMIC_HH__