1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_ATOMIC_HH__
32#define __CPU_SIMPLE_ATOMIC_HH__
33
34#include "cpu/simple/base.hh"
35
36class AtomicSimpleCPU : public BaseSimpleCPU
37{
38 public:
39
40 struct Params : public BaseSimpleCPU::Params {
41 int width;
42 bool simulate_data_stalls;
43 bool simulate_inst_stalls;
44 };
45
46 AtomicSimpleCPU(Params *params);
47 virtual ~AtomicSimpleCPU();
48
49 virtual void init();
50
51 public:
52 //
53 enum Status {
54 Running,
55 Idle,
56 SwitchedOut
57 };
58
59 protected:
60 Status _status;
61
62 Status status() const { return _status; }
63
51 private:
52
53 struct TickEvent : public Event
54 {
55 AtomicSimpleCPU *cpu;
56
57 TickEvent(AtomicSimpleCPU *c);
58 void process();
59 const char *description() const;
60 };
61
62 TickEvent tickEvent;
63
64 const int width;
65 const bool simulate_data_stalls;
66 const bool simulate_inst_stalls;
67
68 // main simulation loop (one cycle)
69 void tick();
70
71 class CpuPort : public Port
72 {
73 public:
74
75 CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
76 : Port(_name, _cpu), cpu(_cpu)
77 { }
78
79 bool snoopRangeSent;
80
81 protected:
82
83 AtomicSimpleCPU *cpu;
84
85 virtual bool recvTiming(PacketPtr pkt);
86
87 virtual Tick recvAtomic(PacketPtr pkt);
88
89 virtual void recvFunctional(PacketPtr pkt);
90
91 virtual void recvStatusChange(Status status);
92
93 virtual void recvRetry();
94
95 virtual void getDeviceAddressRanges(AddrRangeList &resp,
96 bool &snoop)
97 { resp.clear(); snoop = true; }
98
99 };
100 CpuPort icachePort;
101
102 class DcachePort : public CpuPort
103 {
104 public:
105 DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
106 : CpuPort(_name, _cpu)
107 { }
108
109 virtual void setPeer(Port *port);
110 };
111 DcachePort dcachePort;
112
113 CpuPort physmemPort;
114 bool hasPhysMemPort;
115 Request ifetch_req;
116 Request data_read_req;
117 Request data_write_req;
118
119 bool dcache_access;
120 Tick dcache_latency;
121
122 Range<Addr> physMemAddr;
123
124 public:
125
126 virtual Port *getPort(const std::string &if_name, int idx = -1);
127
128 virtual void serialize(std::ostream &os);
129 virtual void unserialize(Checkpoint *cp, const std::string &section);
130 virtual void resume();
131
132 void switchOut();
133 void takeOverFrom(BaseCPU *oldCPU);
134
135 virtual void activateContext(int thread_num, int delay);
136 virtual void suspendContext(int thread_num);
137
138 template <class T>
139 Fault read(Addr addr, T &data, unsigned flags);
140
141 template <class T>
142 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
143
144 Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
145 int size, unsigned flags);
146 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
147 int size, unsigned flags);
148
149 /**
150 * Print state of address in memory system via PrintReq (for
151 * debugging).
152 */
153 void printAddr(Addr a);
154};
155
156#endif // __CPU_SIMPLE_ATOMIC_HH__