1/* 2 * Copyright (c) 2012-2013,2015 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#ifndef __CPU_SIMPLE_ATOMIC_HH__ 44#define __CPU_SIMPLE_ATOMIC_HH__ 45 46#include "cpu/simple/base.hh" 47#include "cpu/simple/exec_context.hh" 48#include "params/AtomicSimpleCPU.hh" 49#include "sim/probe/probe.hh" 50 51class AtomicSimpleCPU : public BaseSimpleCPU 52{ 53 public: 54 55 AtomicSimpleCPU(AtomicSimpleCPUParams *params); 56 virtual ~AtomicSimpleCPU(); 57 58 void init() override; 59 60 private: 61 62 struct TickEvent : public Event 63 { 64 AtomicSimpleCPU *cpu; 65 66 TickEvent(AtomicSimpleCPU *c); 67 void process(); 68 const char *description() const; 69 }; 70 71 TickEvent tickEvent; 72 73 const int width; 74 bool locked; 75 const bool simulate_data_stalls; 76 const bool simulate_inst_stalls; 77 78 // main simulation loop (one cycle) 79 void tick(); 80 81 /** 82 * Check if a system is in a drained state. 83 * 84 * We need to drain if: 85 * <ul> 86 * <li>We are in the middle of a microcode sequence as some CPUs 87 * (e.g., HW accelerated CPUs) can't be started in the middle 88 * of a gem5 microcode sequence. 89 * 90 * <li>The CPU is in a LLSC region. This shouldn't normally happen 91 * as these are executed atomically within a single tick() 92 * call. The only way this can happen at the moment is if 93 * there is an event in the PC event queue that affects the 94 * CPU state while it is in an LLSC region. 95 * 96 * <li>Stay at PC is true. 97 * </ul> 98 */ 99 bool isDrained() { 100 SimpleExecContext &t_info = *threadInfo[curThread]; 101 102 return t_info.thread->microPC() == 0 && 103 !locked && 104 !t_info.stayAtPC; 105 } 106 107 /** 108 * Try to complete a drain request. 109 * 110 * @returns true if the CPU is drained, false otherwise. 111 */ 112 bool tryCompleteDrain(); 113 114 /** 115 * An AtomicCPUPort overrides the default behaviour of the 116 * recvAtomicSnoop and ignores the packet instead of panicking. It 117 * also provides an implementation for the purely virtual timing 118 * functions and panics on either of these. 119 */ 120 class AtomicCPUPort : public MasterPort 121 { 122 123 public: 124 125 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu) 126 : MasterPort(_name, _cpu) 127 { } 128 129 protected: |
130 131 bool recvTimingResp(PacketPtr pkt) 132 { 133 panic("Atomic CPU doesn't expect recvTimingResp!\n"); 134 return true; 135 } 136 137 void recvReqRetry() 138 { 139 panic("Atomic CPU doesn't expect recvRetry!\n"); 140 } 141 142 }; 143 144 class AtomicCPUDPort : public AtomicCPUPort 145 { 146 147 public: 148 149 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) 150 : AtomicCPUPort(_name, _cpu), cpu(_cpu) 151 { 152 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 153 } 154 155 bool isSnooping() const { return true; } 156 157 Addr cacheBlockMask; 158 protected: 159 BaseSimpleCPU *cpu; 160 161 virtual Tick recvAtomicSnoop(PacketPtr pkt); 162 virtual void recvFunctionalSnoop(PacketPtr pkt); 163 }; 164 165 166 AtomicCPUPort icachePort; 167 AtomicCPUDPort dcachePort; 168 169 bool fastmem; 170 Request ifetch_req; 171 Request data_read_req; 172 Request data_write_req; 173 174 bool dcache_access; 175 Tick dcache_latency; 176 177 /** Probe Points. */ 178 ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit; 179 180 protected: 181 182 /** Return a reference to the data port. */ 183 MasterPort &getDataPort() override { return dcachePort; } 184 185 /** Return a reference to the instruction port. */ 186 MasterPort &getInstPort() override { return icachePort; } 187 188 /** Perform snoop for other cpu-local thread contexts. */ 189 void threadSnoop(PacketPtr pkt, ThreadID sender); 190 191 public: 192 193 DrainState drain() override; 194 void drainResume() override; 195 196 void switchOut() override; 197 void takeOverFrom(BaseCPU *oldCPU) override; 198 199 void verifyMemoryMode() const override; 200 201 void activateContext(ThreadID thread_num) override; 202 void suspendContext(ThreadID thread_num) override; 203 204 Fault readMem(Addr addr, uint8_t *data, unsigned size, 205 unsigned flags) override; 206 207 Fault initiateMemRead(Addr addr, unsigned size, unsigned flags) override; 208 209 Fault writeMem(uint8_t *data, unsigned size, 210 Addr addr, unsigned flags, uint64_t *res) override; 211 212 void regProbePoints() override; 213 214 /** 215 * Print state of address in memory system via PrintReq (for 216 * debugging). 217 */ 218 void printAddr(Addr a); 219}; 220 221#endif // __CPU_SIMPLE_ATOMIC_HH__ |